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Tue, 7 Jul 2026 22:29:35 -0700 Date: Tue, 7 Jul 2026 22:29:34 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , "Joerg Roedel (AMD)" , Jean-Philippe Brucker , , Robin Murphy , Will Deacon , David Matlack , "Pasha Tatashin" , , "Pranjal Shrivastava" , Samiullah Khawaja , Mostafa Saleh Subject: Re: [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Message-ID: References: <0-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com> <7-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <7-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E84:EE_|IA5PR12MB999300:EE_ X-MS-Office365-Filtering-Correlation-Id: 763def0c-a2bd-445a-475a-08dedcb1eca0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|7416014|1800799024|376014|36860700016|18002099003|22082099003|4143699003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: raHNQO0VNm6IvJwMhqzGZCM5KC2PIlG7grYVjrgStOp0t0emFXhuXTKWqeap3ZVgItw2BaeTuPRI9uukvvsnWcCDQJsdBZ3D25RjkSPNmICHiDJqshE9j0XM3aGzmnQyhFSSaU0PbCMu7mJiyp5aMCMAilcx/0zz+H9IadOKUoBFbc0R91K9io5jVTDa4gm3Uo25gcza3k2v8lcnzF8Fnn6BbDFWc6wVPIUUvDfkDv5F7TQ1WnaohDRLBhMD3ALT4+sRg7hT7XEuoXG0sw++SLvywlVVswv7NohrFbpiro1/KqtNPLeOhHhh2mYMLAqafTUnDAzw695O1GHIPnhbqi2ELFzpkT4zphFD0OKp+kv/bh0u8df53096mxfpOiZoNLzYQuqQDuFZs0Ax9mUmaBa/ZgKVUt3Y4tLtYp7QdgURJq7LKaylF13aw20tgs/0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2026 05:29:46.9504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 763def0c-a2bd-445a-475a-08dedcb1eca0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E84.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA5PR12MB999300 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260707_222954_403195_822E5E34 X-CRM114-Status: GOOD ( 17.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 06, 2026 at 01:26:44PM -0300, Jason Gunthorpe wrote: > + * Compute the stride for non-RIL single-page invalidation. Returns the log2 > + * stride of the lowest affected level. Single invalidation removes all IOPTEs > + * that contain the IOVA invalidated, and we can reliably assume that the > + * architected page size and table sizes (not contiguous!) are reflected in the > + * IOTLB. Thus if there is a 2M leaf entry we only need to issue a single IOTLB > + * invalidation within that 2M IOVA. > + */ > +static u8 arm_smmu_tlbi_calc_stride(struct arm_smmu_tlbi *tlbi) > +{ > + unsigned int tg_lg2 = tlbi->smmu_domain->tgsz_lg2; > + u8 combined = tlbi->table_levels_bitmap | tlbi->leaf_levels_bitmap; > + > + if (!combined) > + return U8_MAX; > + return (tg_lg2 - 3) * __ffs(combined) + tg_lg2; > +} > + > +/* > + * One TLBI command per stride-sized entry. Sets use_full_inv if too many This is raised by Claude; not sure whether it is a false positive or not. This changes a previous per-pte invalidation to per-pmd one. Yet, the spec states in 4.4 TLB invalidation (last paragraph): To match a TLB entry, the least significant bits of the address are ignored as needed, given the size of the entry. So, the following scenario would likely miss leaf entries: VFIO_IOMMU_UNMAP_DMA / IOMMU_IOAS_UNMAP iommu_unmap(domain, iova=0x40000000, size=2M) __iommu_unmap() iommu_pgsize() -> picks pgsize=2M (aligned, 2M in pgsize_bitmap; irrelevant that the region was mapped as 4K pages) arm_lpae_unmap_pages(iova, 2M, pgcount=1, gather) __arm_lpae_unmap(lvl=0) -> lvl=1 -> lvl=2: size == BLOCK_SIZE(lvl 2) pte = READ_ONCE(*ptep) -> a TABLE descriptor, not a block __arm_lpae_clear_pte() # L2 descriptor := 0 io_pgtable_tlb_flush_walk(iova, 2M, granule=4K) arm_smmu_tlb_inv_walk() tlbi = { start=0x40000000, last=0x401fffff, table_levels_bitmap = BIT((ilog2(2M)-12)/9) = 0b010, leaf_levels_bitmap = 0 } <-- the false claim arm_smmu_domain_tlbi() arm_smmu_tlbi_calc_single(): calc_stride: __ffs(0b010) = 1 -> stride = 2M num_ops = 2M >> 21 = 1 arm_smmu_domain_tlbi_inv() non-RIL entry: ONE TLBI_NH_VA @0x40000000, Leaf=0 -> kills the walk entry + the 4K leaf at base -> 511 4K leaves SURVIVE __arm_lpae_free_pgtable() # subtree freed, no invalidation iommu_iotlb_sync(domain, &gather) # gather->pgsize == 0 -> returns immediately > + * If leaf_levels_bitmap is 0 then this is a walk cache only > + * invalidation. [...] > + u8 leaf_levels_bitmap; Or is that only to implement a walkcache-only invalidation, such that the leaf entries will have separate invalidation call(s)? Nicolin