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X-CSE-ConnectionGUID: FmhYdmoMQvKIwl7auYgdPA== X-CSE-MsgGUID: JZ7Vj+xARQGuF+UCPT9hVQ== X-IronPort-AV: E=McAfee;i="6800,10657,11832"; a="82521280" X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="82521280" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 05:16:39 -0700 X-CSE-ConnectionGUID: dJEhJRdtTxqOgFFYZ+iaZg== X-CSE-MsgGUID: yA1VguZ+QZukmHFHt/ditg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="276531891" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.96]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 05:16:33 -0700 Date: Tue, 30 Jun 2026 15:16:31 +0300 From: Andy Shevchenko To: Varshini Rajendran Cc: ehristev@kernel.org, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, srini@kernel.org, marcelo.schmitt@analog.com, jorge.marques@analog.com, mazziesaccount@gmail.com, Jonathan.Santos@analog.com, jishnu.prakash@oss.qualcomm.com, antoniu.miclaus@analog.com, duje@dujemihanovic.xyz, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 03/13] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling Message-ID: References: <20260630093603.38663-1-varshini.rajendran@microchip.com> <20260630093603.38663-4-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260630093603.38663-4-varshini.rajendran@microchip.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260630_051639_341330_3CA6D92E X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jun 30, 2026 at 03:05:53PM +0530, Varshini Rajendran wrote: > Extend support to handle different temperature calibration layouts. > > Add a temperature calibration data layout structure to describe indexes > of the factors P1, P4, P6, tag, minimum length of the packet and the > scaling factors for P1 (mul, div) which are SoC-specific instead of the > older non scalable id structure. This helps handle the differences in the > same function flow and prepare the calibration data to be applied. Add > additional condition to validate the calibration data read from the > NVMEM cell using the TAG of the packet. ... > /** > * struct at91_adc_platform - at91-sama5d2 platform information struct > * @layout: pointer to the reg layout struct > * @oversampling_avail_no: number of available oversampling values > * @chan_realbits: realbits for registered channels > * @temp_chan: temperature channel index > + * @temp_calib_layout: temperature calibration packet layout This uses spaces instead of tab(s). > * @temp_sensor: temperature sensor supported > */ ... > + layout = st->soc_info.platform->temp_calib_layout; > + if (!layout || !layout->p1_div) Technically speaking the !layout condition rather means -ENODEV. > + return -EINVAL; ... > + clb->p1 *= layout->p1_mul; > + clb->p1 /= layout->p1_div; So, p1 can be defined in layout as struct u32_fract. -- With Best Regards, Andy Shevchenko