From: Vsevolod Kozlov <zaba@mm.st>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
David Petry <petry103@gmail.com>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: rockchip: fan speed control for FriendlyELEC CM3588 NAS
Date: Sat, 4 Jul 2026 15:46:52 +0300 [thread overview]
Message-ID: <akkAvJap-MtbKp8B@Vsevolods-MacBook-Pro.local> (raw)
The FriendlyELEC CM3588 NAS kit is often supplied with a case and a fan.
Enable control of the speed of the fan using the trip points and cooling
maps from rk3588-nanopc-t6.dtsi as a reference.
Signed-off-by: Vsevolod Kozlov <zaba@mm.st>
---
.../rk3588-friendlyelec-cm3588-nas.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
index 0dce96ca8c28..f4c34da61c4d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588-friendlyelec-cm3588.dtsi"
@@ -457,6 +458,36 @@ &i2c8 {
status = "okay";
};
+&package_thermal {
+ polling-delay = <1000>;
+
+ trips {
+ package_warm: package-warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ package_hot: package-hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&package_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map1 {
+ trip = <&package_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&pcie2x1l0 {
/* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */
max-link-speed = <3>;
--
2.47.3
reply other threads:[~2026-07-04 12:47 UTC|newest]
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