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From: Oliver Upton <oupton@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	Steffen Eiden <seiden@linux.ibm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v2 2/6] KVM: arm64: Move GICv3 broken SEIS implementation detection to a CPU errrata
Date: Tue, 21 Jul 2026 10:57:23 -0700	[thread overview]
Message-ID: <al-zA7eek869owmN@kernel.org> (raw)
In-Reply-To: <20260721170754.3150521-3-maz@kernel.org>

Hey,

On Tue, Jul 21, 2026 at 06:07:50PM +0100, Marc Zyngier wrote:
> Using is_midr_in_range_list() in a noinstr function isn't a good idea.
> And yet kvm_compute_ich_hcr_trap_bits() is doing that by calling
> vgic_v3_broken_seis().
> 
> Move all the broken SEIS detection logic to the errata detection
> framework, and use a new ARM64_WORKAROUND_GICv3_BROKEN_SEIS cap
> to indicate that we're running on broken CPUs.
> 
> This reuses the MIDR list used for IMPDEF PMU detection, which
> has a 100% overlap with the SEIS stuff...

Hopefully this remains the case! Oh well, that's the next person's
problem to sort out anyway.

Thanks,
Oliver

> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/kernel/cpu_errata.c | 17 +++++++++++++++--
>  arch/arm64/kvm/vgic/vgic-v3.c  | 26 +++-----------------------
>  arch/arm64/tools/cpucaps       |  1 +
>  3 files changed, 19 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 1995e1198648e..78e4e105f6ab5 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -272,7 +272,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
>  	return is_midr_in_range(&range) && has_dic;
>  }
>  
> -static const struct midr_range impdef_pmuv3_cpus[] = {
> +static const struct midr_range apple_cpus[] = {
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
> @@ -301,7 +301,14 @@ static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int sco
>  	if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
>  		return false;
>  
> -	return is_midr_in_range_list(impdef_pmuv3_cpus);
> +	return is_midr_in_range_list(apple_cpus);
> +}
> +
> +static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope)
> +{
> +	return (is_kernel_in_hyp_mode() &&
> +		is_midr_in_range_list(apple_cpus) &&
> +		(read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS));
>  }
>  
>  static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused)
> @@ -1009,6 +1016,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>  		.matches = has_impdef_pmuv3,
>  		.cpu_enable = cpu_enable_impdef_pmuv3_traps,
>  	},
> +	{
> +		.desc = "Known broken GICv3 SEIS implementation",
> +		.capability = ARM64_WORKAROUND_GICv3_BROKEN_SEIS,
> +		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
> +		.matches = has_broken_gic_v3_seis,
> +	},
>  	{
>  	}
>  };
> diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
> index 9e841e7afd4a7..0991a649a5d1e 100644
> --- a/arch/arm64/kvm/vgic/vgic-v3.c
> +++ b/arch/arm64/kvm/vgic/vgic-v3.c
> @@ -809,27 +809,9 @@ static int __init early_gicv4_enable(char *buf)
>  }
>  early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
>  
> -static const struct midr_range broken_seis[] = {
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
> -	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
> -	{},
> -};
> -
> -static bool vgic_v3_broken_seis(void)
> +static __always_inline bool vgic_v3_broken_seis(void)
>  {
> -	return (is_kernel_in_hyp_mode() &&
> -		is_midr_in_range_list(broken_seis) &&
> -		(read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS));
> +	return cpus_have_cap(ARM64_WORKAROUND_GICv3_BROKEN_SEIS);
>  }
>  
>  void noinstr kvm_compute_ich_hcr_trap_bits(struct alt_instr *alt,
> @@ -959,10 +941,8 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
>  	if (has_v2)
>  		static_branch_enable(&vgic_v3_has_v2_compat);
>  
> -	if (vgic_v3_broken_seis()) {
> -		kvm_info("GICv3 with broken locally generated SEI\n");
> +	if (vgic_v3_broken_seis())
>  		kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_EL2_SEIS;
> -	}
>  
>  	vgic_v3_enable_cpuif_traps();
>  
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 9b85a84f6fd49..50373264ecde8 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -121,6 +121,7 @@ WORKAROUND_CAVIUM_TX2_219_TVM
>  WORKAROUND_CLEAN_CACHE
>  WORKAROUND_DEVICE_LOAD_ACQUIRE
>  WORKAROUND_DISABLE_CNP
> +WORKAROUND_GICv3_BROKEN_SEIS
>  WORKAROUND_PMUV3_IMPDEF_TRAPS
>  WORKAROUND_QCOM_FALKOR_E1003
>  WORKAROUND_QCOM_ORYON_CNTVOFF
> -- 
> 2.47.3
> 


  reply	other threads:[~2026-07-21 17:57 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21 17:07 [PATCH v2 0/6] KVM: arm64: Make ICH_VTR_EL2 accesses an inlined literal Marc Zyngier
2026-07-21 17:07 ` [PATCH v2 1/6] KVM: arm64: vgic-v3: Make vtr_to_* helpers use architectural field symbols Marc Zyngier
2026-07-21 17:07 ` [PATCH v2 2/6] KVM: arm64: Move GICv3 broken SEIS implementation detection to a CPU errrata Marc Zyngier
2026-07-21 17:57   ` Oliver Upton [this message]
2026-07-21 17:07 ` [PATCH v2 3/6] KVM: arm64: Add a helper providing an inlined literal value for ICH_VTR_EL2 Marc Zyngier
2026-07-21 17:07 ` [PATCH v2 4/6] KVM: arm64: Convert most ICH_VTR_EL2 accesses to inlined literal value Marc Zyngier
2026-07-21 17:07 ` [PATCH v2 5/6] KVM: arm64: vgic-v3: Simplify initial GICv3 configuration sampling Marc Zyngier
2026-07-21 17:07 ` [PATCH v2 6/6] KVM: arm64: vgic-v3: Kill kvm_vgic_global_state.ich_vtr_el2 Marc Zyngier
2026-07-21 18:24 ` [PATCH v2 0/6] KVM: arm64: Make ICH_VTR_EL2 accesses an inlined literal Oliver Upton

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