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[34.76.60.220]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47aa0f214d2sm82275582f8f.33.2026.07.13.04.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 04:07:52 -0700 (PDT) Date: Mon, 13 Jul 2026 11:07:48 +0000 From: Mostafa Saleh To: Vincent Donnefort Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jean-philippe@linaro.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, sebastianene@google.com, keirf@google.com Subject: Re: [PATCH v6 16/25] iommu/arm-smmu-v3-kvm: Add CMDQ functions Message-ID: References: <20260501111928.259252-1-smostafa@google.com> <20260501111928.259252-17-smostafa@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260713_040756_031371_C81E110B X-CRM114-Status: GOOD ( 26.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 10, 2026 at 05:01:07PM +0100, Vincent Donnefort wrote: > On Fri, May 01, 2026 at 11:19:18AM +0000, Mostafa Saleh wrote: > > Add functions to access the command queue, there are 2 main usage: > > - Hypervisor's own commands, as TLB invalidation, would use functions > > as smmu_send_cmd(), which creates and sends a command. > > - Add host commands to the shadow command queue, after being filtered, > > these will be added with smmu_add_cmd_raw. > > > > Signed-off-by: Mostafa Saleh > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 14 ++- > > .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 107 ++++++++++++++++++ > > 2 files changed, 115 insertions(+), 6 deletions(-) > > [...] > > I only looked at that smmu_wait() as this is the hyp_clock_ns() caller. > > > > > +/* > > + * Wait until @cond is true. > > + * Return 0 on success, or -ETIMEDOUT > > nit: Would be nice to explain use_wfe. I will add it. > > > + */ > > +#define smmu_wait(use_wfe, _cond) \ > > nit:, (__use_wfe, __cond), or (use_fw, cond) Will do. > > > +({ \ > > + int __ret = 0; \ > > + u64 delay = hyp_clock_ns() + ARM_SMMU_POLL_TIMEOUT_US * 1000; \ > > Does it help to lower the risk for the 128-bits fallback if we keep the > resolution to _us? I will remove the tracing clock support as mentioned and I will handle the overflow in smmu_wait() > > Also, ARM_SMMU_POLL_TIMEOUT_US seems to be 1s. Blocking that long at EL2 is > really terrible. Any chance to lower that? > That should never really happen, I am re-using the kernel max, but I can change this for the hypervisor. > > + \ > > + while (!(_cond)) { \ > > + if (use_wfe) { \ > > + wfe(); \ > > + if ((_cond)) \ > > nit: I believe there's no need for the double () here is there? > Will do. Thanks, Mostafa