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charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260714_064311_866610_C3E773DB X-CRM114-Status: GOOD ( 18.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 08, 2026 at 03:53:59PM +0100, Suzuki K Poulose wrote: > On 08/07/2026 15:43, Linu Cherian wrote: > > Add below cpus to the midr list, which supports > > BBML2_NOABORT. > > > > Cortex A520(AE) > > Cortex A715 > > Cortex A720(AE) > > Cortex A725 > > Neoverse N3 > > C1-Nano > > C1-Pro > > C1-Ultra > > C1-Premium > > > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > > where Break-Before-Make must be followed to avoid a livelock. > > For both CPUs, the erratum is fixed from r1p1. > > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > Please could you also update the list of errata here : > > Documentation/arch/arm64/silicon-errata.rst Ack. > > > > > The relevant SDENs are: > > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ > > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ > > > > Signed-off-by: Linu Cherian > > --- > > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 9a22df0c5120..adcabea80fcb 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void) > > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > > And mention it here, so that it is evident from the code alone ? > Ack. > > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > > > Suzuki > > > > {} > > }; >