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From: Linu Cherian <linu.cherian@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID
Date: Tue, 14 Jul 2026 19:31:01 +0530	[thread overview]
Message-ID: <alZBHSLOLIelWM-d@a079125.arm.com> (raw)
In-Reply-To: <11d99a7c-50f9-4a4d-a75b-ef11cf3371af@arm.com>

Hi,

On Fri, Jul 10, 2026 at 12:41:57PM +0530, Anshuman Khandual wrote:
> Please do mention full register field here
> 
> arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM
> 
> On 08/07/26 8:13 PM, Linu Cherian wrote:
> > Add MMFR2 ID based BBML3 feature detection, so
> 
> Ditto ^^^^^^^^^^^^
> 
> > that compliant cpus doesn't need to be added to the
> > midr list.
> 
> Could be reworded as :
> 
> Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in
> cpu_supports_bbml3() so that cpus with the feature would
> not have to be added into MIDR based supports_bbml3_list.
> 

Okay, will change.


> > 
> > Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> > ---
> >  arch/arm64/kernel/cpufeature.c | 17 +++++++++--------
> >  1 file changed, 9 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index e9ecaa036479..3f4a36f152d0 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
> >  
> >  bool cpu_supports_bbml3(void)
> >  {
> > +	u64 mmfr2;
> > +
> > +	mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1);
> > +	if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3)
> > +		return true;
> > +
> >  	/* CPUs that support BBML3 but dont advertise through MMFR2 ID */
> >  	static const struct midr_range supports_bbml3_list[] = {
> >  		MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
> > @@ -2153,15 +2159,10 @@ bool cpu_supports_bbml3(void)
> >  		{}
> >  	};
> >  
> > -	if (!is_midr_in_range_list(supports_bbml3_list))
> > -		return false;
> > -
> > -	/*
> > -	 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care
> > -	 * about whether the MIDR check passes.
> > -	 */
> > +	if (is_midr_in_range_list(supports_bbml3_list))
> > +		return true;
> >  
> > -	return true;
> > +	return false;
> >  }
> >  
> >  static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope)
> 
> With the minor changes to the commit message above.
> 
> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>


      reply	other threads:[~2026-07-14 14:01 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08 14:43 [PATCH v2 0/6] Add BBML3 cpu feature Linu Cherian
2026-07-08 14:43 ` [PATCH v2 1/6] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-10  6:37   ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions Linu Cherian
2026-07-10  6:37   ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list Linu Cherian
2026-07-08 14:53   ` Suzuki K Poulose
2026-07-10  6:24     ` Anshuman Khandual
2026-07-14 13:43     ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 4/6] arm64: sysreg: Add BBM_3 Linu Cherian
2026-07-10  6:46   ` Anshuman Khandual
2026-07-15  3:27     ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 5/6] arm64: cpufeature: Add BBML3 Linu Cherian
2026-07-10  7:00   ` Anshuman Khandual
2026-07-14 13:59     ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Linu Cherian
2026-07-10  7:11   ` Anshuman Khandual
2026-07-14 14:01     ` Linu Cherian [this message]

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