From mboxrd@z Thu Jan  1 00:00:00 1970
From: cl@linux.com (Christoph Lameter)
Date: Fri, 10 Dec 2010 15:09:08 -0600 (CST)
Subject: [BUG] 2.6.37-rc3 massive interactivity regression on ARM
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Message-ID: <alpine.DEB.2.00.1012101505250.13986@router.home>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On Fri, 10 Dec 2010, Eric Dumazet wrote:

>
> By the way, we need smp_wmb(), not barrier(), even only the "owner cpu"
> can write into its 'percpu' seqcount.
>
> There is nothing special about a seqcount being percpu or a 'global'
> one. We must have same memory barrier semantics.

There is certainly a major difference in that execution of a stream of
instructions on the same cpu is guaranteed to have a coherent view of
the data. That is not affected by interrupts etc.

>
> 	this_cpu_write_seqcount_begin(&myseqcount);
> 	this_cpu_add(mydata1, add1);
> 	this_cpu_add(mydata2, add2);
> 	this_cpu_inc(mydata3);
> 	this_cpu_write_seqcount_end(&myseqcount);
>
> We protect the data[1,2,3] set with a seqcount, so need smp_wmb() in
> both _begin() and _end()

There is nothing to protect there since processing is on the same cpu. The
data coherency guarantees of the processor will not allow anything out of
sequence to affect execution. An interrupt f.e. will not cause updates to
mydata1 to get lost.