From: pwalmsley@nvidia.com (Paul Walmsley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file
Date: Mon, 13 Jan 2014 22:36:21 -0800 [thread overview]
Message-ID: <alpine.DEB.2.02.1401132233450.11672@tamien> (raw)
In-Reply-To: <52B38AE9.2030209@wwwdotorg.org>
On Thu, 19 Dec 2013, Stephen Warren wrote:
> On 12/19/2013 05:49 AM, Paul Walmsley wrote:
>> Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect
>> the DFLL (and FCPU cluster) voltage regulator.
>
>> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt
>
>> +NVIDIA Tegra114 DFLL clocksource data in the board DTS file
>> +
>> +Optional properties:
>> +
>> +- status : device availability -- managed by the DT integration code, not
>> + the DFLL driver. Should be set to "okay" if the DFLL is to be
>> + used on this board type.
>
> There's certainly no need to document the same DT property twice.
I've just dropped this section, per your earlier suggestion.
- Paul
next prev parent reply other threads:[~2014-01-14 6:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-19 12:36 [PATCH 0/6] clk: tegra: add basic support for the DFLL clocksource Paul Walmsley
2013-12-19 12:36 ` [PATCH 1/6] ARM: tegra: fuse: add functions to read speedo ID and process ID Paul Walmsley
2013-12-19 23:09 ` Stephen Warren
2013-12-19 12:36 ` [PATCH 2/6] ARM: tegra114: fuse: add DFLL FCPU minimum voltage override test function Paul Walmsley
2013-12-19 23:12 ` Stephen Warren
2013-12-19 12:37 ` [PATCH 3/6] clk: tegra: add library for the DFLL clocksource (open-loop mode) Paul Walmsley
2013-12-19 23:57 ` Stephen Warren
2013-12-19 12:49 ` [PATCH 4/6] ARM: DTS: tegra: add the DFLL IP block to the T114 SoC file Paul Walmsley
2013-12-20 0:05 ` Stephen Warren
2014-01-14 6:27 ` Paul Walmsley
2014-01-14 6:32 ` Paul Walmsley
2014-01-15 19:50 ` Gerhard Sittig
2014-01-15 20:09 ` Paul Walmsley
[not found] ` <52D4D314.3000208@nvidia.com>
2014-01-14 17:43 ` Stephen Warren
2013-12-19 12:49 ` [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file Paul Walmsley
2013-12-20 0:10 ` Stephen Warren
2014-01-14 6:36 ` Paul Walmsley [this message]
2013-12-19 12:49 ` [PATCH 6/6] clk: tegra: add Tegra114 FCPU DFLL clocksource platform driver Paul Walmsley
2013-12-20 0:18 ` Stephen Warren
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