From: tglx@linutronix.de (Thomas Gleixner)
To: linux-arm-kernel@lists.infradead.org
Subject: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)
Date: Mon, 3 Nov 2014 23:51:43 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.11.1411032300160.5308@nanos> (raw)
In-Reply-To: <1415052977-26036-3-git-send-email-suravee.suthikulpanit@amd.com>
On Mon, 3 Nov 2014, suravee.suthikulpanit at amd.com wrote:
> +static void gicv2m_teardown_msi_irq(struct msi_chip *chip, unsigned int irq)
> +{
> + int pos;
> + struct v2m_data *v2m = container_of(chip, struct v2m_data, msi_chip);
> +
> + spin_lock(&v2m->msi_cnt_lock);
Why do you need an extra lock here? Is that stuff not serialized from
the msi_chip layer already?
If not, why don't we have the serialization there instead of forcing
every callback to implement its own?
> + pos = irq - v2m->spi_start;
So this assumes that @irq is the hwirq number, right? How does the
calling function know about that? It should only have knowledge about
the virq number if I'm not missing something.
And if I'm missing something, then that msi_chip stuff is seriously
broken.
> + if (pos >= 0 && pos < v2m->nr_spis)
So you simply avoid the clear bitmap instead of yelling loudly about
being called with completely wrong data?
I would not be surprised if that is related to my question above.
> + bitmap_clear(v2m->bm, pos, 1);
> +static int gicv2m_setup_msi_irq(struct msi_chip *chip, struct pci_dev *pdev,
> + struct msi_desc *desc)
> +{
> + int hwirq, virq, offset;
> + struct v2m_data *v2m = container_of(chip, struct v2m_data, msi_chip);
> +
> + if (!desc)
> + return -EINVAL;
Why on earth does every callback of msi_chip have to check for this?
> + spin_lock(&v2m->msi_cnt_lock);
> + offset = bitmap_find_free_region(v2m->bm, v2m->nr_spis, 0);
> + spin_unlock(&v2m->msi_cnt_lock);
> + if (offset < 0)
> + return offset;
> +
> + hwirq = v2m->spi_start + offset;
> + virq = __irq_domain_alloc_irqs(v2m->domain, hwirq,
> + 1, NUMA_NO_NODE, v2m, true);
> + if (virq < 0) {
> + gicv2m_teardown_msi_irq(chip, hwirq);
> + return virq;
> + }
> +
> + irq_domain_set_hwirq_and_chip(v2m->domain, virq, hwirq,
> + &v2m_chip, v2m);
> +
> + irq_set_msi_desc(hwirq, desc);
> + irq_set_irq_type(hwirq, IRQ_TYPE_EDGE_RISING);
Sure both calls work perfectly fine as long as virq == hwirq, right?
> + return 0;
Q: How does this populate virq to the caller?
A: Not at all
Q: How does the caller know which virq this function assigned?
A: Not at all
Q: How does the device driver know which virq to request?
A: Not at all
Q: Was this patch ever properly tested?
A: Not at all.
I do not care at all how YOU waste your time. But I care very much
about the fact that YOU are wasting MY precious time by exposing me to
your patch trainwrecks.
Thanks,
tglx
next prev parent reply other threads:[~2014-11-03 22:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-03 22:16 [V10 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support suravee.suthikulpanit at amd.com
2014-11-03 22:16 ` [V10 PATCH 1/2] genirq: Add irq_chip_set_type_parent function suravee.suthikulpanit at amd.com
2014-11-03 22:16 ` [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X) suravee.suthikulpanit at amd.com
2014-11-03 22:51 ` Thomas Gleixner [this message]
2014-11-04 3:22 ` Suravee Suthikulanit
2014-11-04 10:06 ` Thomas Gleixner
2014-11-04 14:20 ` Suravee Suthikulpanit
2014-11-04 14:28 ` Thomas Gleixner
2014-11-04 17:46 ` Marc Zyngier
2014-11-04 13:01 ` Jiang Liu
2014-11-04 17:00 ` Suravee Suthikulpanit
2014-11-06 0:05 ` Suravee Suthikulanit
2014-11-06 0:23 ` Suravee Suthikulanit
2014-11-06 0:49 ` Thomas Gleixner
2014-11-06 10:42 ` Thomas Gleixner
2014-11-06 16:34 ` Marc Zyngier
2014-11-07 1:00 ` Jiang Liu
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