[PATCH 05/10] clk: Add support for simple dividers

Richard Zhao
2011-04-26T01:54:37Z

On Mon, Apr 25, 2011 at 08:51:13PM +0200, Sascha Hauer wrote:
> On Sun, Apr 24, 2011 at 09:48:33PM +0800, Richard Zhao wrote:
> > > +
> > > + div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
> > > +
> > > + if (rate != best_parent_rate / div)
> > > + return -EINVAL;
> > > +
> > > + ret = clk_set_rate(divider->parent, best_parent_rate);
> > why do you set parent rate? It may impact hte parent's other children.
> >
>
> In a newer version I already created a barrier flag for not setting the
> parents rate. Setting the parents rate is needed for for example
> cascaded dividers. Otherwise this could be much simpler.
And do you find a way to let clock actual parents indepent on reset or uboot
register settings. If we can register clk, maybe:
if (clk->ops.hw_get_parent)
clk->parent = clk->ops->hw_get_parent;

Thanks
Richard
>
> Sascha
>
>
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