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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a07d38318esm414754a12.19.2026.07.30.02.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 02:30:09 -0700 (PDT) Date: Thu, 30 Jul 2026 09:30:05 +0000 From: Mostafa Saleh To: Linu Cherian Cc: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org, oupton@kernel.org, seiden@linux.ibm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, vdonnefort@google.com, tabba@google.com, sebastianene@google.com, keirf@google.com Subject: Re: [RFC PATCH v2 0/2] KVM: arm64: Add support for BBM level 3 Message-ID: References: <20260723182140.4025575-1-smostafa@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260730_023013_606122_B30E9A20 X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Linu, On Thu, Jul 30, 2026 at 08:52:37AM +0530, Linu Cherian wrote: > Hi, > > On Thu, Jul 23, 2026 at 06:21:38PM +0000, Mostafa Saleh wrote: > > This patch series adds support for BBM level 3 to KVM pgtable, it > > depends on [1] > > > > Changes from v1: > > https://lore.kernel.org/all/20260717130901.2239134-1-smostafa@google.com/ > > - Limit BBML3 to systems with FWB and DIC and remove race check. > > > > Motivation > > ========== > > I have been looking into this for the context of: > > - Page table sharing between the host CPU stage-2 and the SMMUv3 for > > protected KVM. > > - Use the pagtable code to populate SMMUv3 stage-2 shadowed > > page table [2] > > > > However, BBM level 3 is still useful for CPU only operations as it > > avoids intermediately breaking translation. > > > > Design > > ====== > > Some of the conditions that BBM level 3 will be useful in (RWHZWS): > > 1) A change to a PTE memory type, shareability, cacheability or OA > > Could you please clarify how BBM level 3 is helping this particular scenario ? > This is supposed to be a case where break before make is required. Right, I initially misinterpreted the rule. However, AFAIK, KVM does not rely on those, I added a comment based on Oliver feedback in the last version. I will update the cover letter. But looking again, may be we also need an extra check to enforce that in the run time and fallback to SW BBM as I'd be concerned about some of the KVM call chains as user_mem_abort(). Thanks, Mostafa > > Thanks, > Linu Cherian. >