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Mon, 10 Aug 2026 20:50:35 -0700 (PDT) Received: from blinky ([67.174.242.98]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-392d4050557sm1740457a91.3.2026.08.10.20.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 20:50:34 -0700 (PDT) Date: Mon, 10 Aug 2026 20:50:31 -0700 From: Charlie Jenkins To: Atish Patra Cc: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Ian Rogers , Will Deacon , James Clark , linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley Subject: Re: [PATCH v8 12/22] RISC-V: perf: Modify the counter discovery mechanism Message-ID: References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> <20260701-counter_delegation-v8-12-7909f863a645@meta.com> <178453211938.543975.7016109597042850635.b4-review@b4> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260810_205036_834132_04A20F6C X-CRM114-Status: GOOD ( 31.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 07, 2026 at 01:08:31AM -0700, Atish Patra wrote: > > On 7/20/26 12:21 AM, Charlie Jenkins wrote: > > On Wed, 01 Jul 2026 01:47:00 -0700, Atish Patra wrote: > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > > index 74d934238821..c20f1e33c65d 100644 > > > --- a/drivers/perf/riscv_pmu_sbi.c > > > +++ b/drivers/perf/riscv_pmu_sbi.c > > > @@ -1599,13 +1658,23 @@ static int __init rvpmu_devinit(void) > > > [ ... skip 15 lines ... ] > > > + * in S-mode via Supervisor Counter delegation. > > > + */ > > > + if (riscv_isa_extension_available(NULL, SSCCFG) && > > > + riscv_isa_extension_available(NULL, SMCDELEG) && > > > + riscv_isa_extension_available(NULL, SSCSRIND)) > > > + static_branch_enable(&riscv_pmu_cdeleg_available); > > This needs to not only check that smcdeleg is supported in linux, but > > also that it is supported in the SBI implementation correct? Trying to > > boot this on OpenSBI before 6bb6b61c27eb ("lib: sbi: Add support for smcsrind and > > smcdeleg") will fail on an illegal instruction in > > rvpmu_deleg_find_ctrs() while trying to access the scountinhibit csr in > > the patch "RISC-V: perf: Implement supervisor counter delegation > > support". The proper mstateen bits need to be set for this to work > > without crashing. > > Yeah. We can do trap/detect to identify if smcdeleg is actually available > but that is bit ugly. > The firmware should make sure that it doesn't advertises an ISA extension if > that is not avaialble > to S-mode but that model only works for newer firmware. > > if you are running very old firmware with new Qemu/platform, the default ISA > extension may have > smcdeleg while older firmware may not even know about it. > > In reality, I am hoping chances of that happening are rare as OpenSBI > patches have been available > from a long time and Linux kernel patches are yet to merge. I have not > addressed this in v9 as I am > not sure which is the best worst approach yet :) I had an old opensbi binary laying around and ran into this. This unfortunately crashes the kernel, but since there is not a good way of detecting it and newer firmware has handled it for 2 years now, I think it is acceptable to leave this as-is. - Charlie > > >