Re: [PATCH v2 2/2] irqchip/gic-v5: Synchronize CPU interface disable

[Lorenzo Pieralisi <lpieralisi@kernel.org>]

On Tue, Aug 11, 2026 at 03:27:31PM +0000, Sascha Bischoff wrote:
> The write disabling the GICv5 CPU interface is only guaranteed to take
> effect after a context synchronization event. Without one, execution can
> return from gicv5_cpu_disable_interrupts() while an interrupt is still
> able to be taken.
> 
> Add an ISB after the ICC_CR0_EL1 write to ensure interrupts are
> disabled before the function returns. No corresponding ISB is added
> when enabling the interface, as interrupt delivery is asynchronous and
> there is no obvious benefit to waiting for it.
> 
> Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support")
> Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=6
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
>  drivers/irqchip/irq-gic-v5.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

> diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
> index e9d1795235a66..6a99c541b559b 100644
> --- a/drivers/irqchip/irq-gic-v5.c
> +++ b/drivers/irqchip/irq-gic-v5.c
> @@ -983,6 +983,7 @@ static void gicv5_cpu_disable_interrupts(void)
>  
>  	cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0);
>  	write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
> +	isb();
>  }
>  
>  static void gicv5_cpu_enable_interrupts(void)
> -- 
> 2.34.1