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X-CSE-ConnectionGUID: WtsynNS7QhOsCBbgexMdZw== X-CSE-MsgGUID: 8y/+IQ1gTbe8FoiF/Ay5hw== X-IronPort-AV: E=McAfee;i="6800,10657,11879"; a="87646173" X-IronPort-AV: E=Sophos;i="6.25,231,1779174000"; d="scan'208";a="87646173" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2026 00:27:52 -0700 X-CSE-ConnectionGUID: J+3m20rtSdqiMKQ+W6sX2Q== X-CSE-MsgGUID: i+ywqdASR2ib4M2LXoSg4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,231,1779174000"; d="scan'208";a="269303976" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.244.106]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2026 00:27:46 -0700 Date: Wed, 19 Aug 2026 10:27:43 +0300 From: Andy Shevchenko To: zl020895 Cc: longzhao , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc , linux-arm-kernel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Catalin Marinas , Will Deacon , devicetree , linux-clk , linux-gpio , linux-serial , linux-kernel , Brian Masney , Lee Jones , mfd Subject: Re: Re: [PATCH v5 08/12] gpio: pl061: add Ambarella CV75 register layout variant Message-ID: References: <20260818-cv75-v5-v5-0-7bbb12f0360f@ambarella.com> <20260818-cv75-v5-v5-8-7bbb12f0360f@ambarella.com> <79f6dc8c.2c42c.1a018dadd29.Coremail.zl020895@163.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <79f6dc8c.2c42c.1a018dadd29.Coremail.zl020895@163.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260819_002754_032665_CCB21C47 X-CRM114-Status: GOOD ( 21.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 19, 2026 at 03:09:51PM +0800, zl020895 wrote: > > I followed Linus' guidance on the v2 pinctrl patch to reuse gpio-pl061 with a > per-variant register layout, because the Ambarella banks share the PL061 > interrupt register model (IS/IBE/IEV/IE/RIS/MIS/IC). gpio-mmio/gpio-regmap > cover the DATA/DIR side well, but they seem not provide that IRQ controller, > so moving there would need a separate irqchip and would risk duplicating the > PL061 IRQ logic Linus asked us not to fork. > > > Would you prefer we keep the PL061 variant for that reason, or is there a > gpio-mmio/gpio-regmap approach that also covers this interrupt model cleanly? > We can rework either way once that is clear. I haven't told we should duplicate. My suggestion is: - convert current gpio-pl061 to use gpio-mmio / gpio-regmap (and I vote for the latter) - add new regmap configuration and necessary layout for your case. > ---- Replied Message ---- > | From | Andy Shevchenko | > | Date | 08/18/2026 22:11 | > On Tue, Aug 18, 2026 at 06:31:22PM +0800, Long Zhao via B4 Relay wrote: > > > Extend gpio-pl061 with a per-variant register layout so the Ambarella > > CV75 GPIO banks can reuse the PL061 driver instead of a duplicate. > > This is reinvention of gpio-mmio.c (as a library). It has necessary facilities. > Also gpio-regmap may be considered. So, switch this driver to use one of the > above and the patch for the new device will be much simpler and elegant. -- With Best Regards, Andy Shevchenko