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[104.155.91.135]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce551bf7asm40161205e9.2.2026.09.02.08.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 08:05:16 -0700 (PDT) Date: Wed, 2 Sep 2026 16:05:12 +0100 From: Vincent Donnefort To: Fuad Tabba Cc: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas , Will Deacon , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Quentin Perret , Fuad Tabba Subject: Re: [PATCH 05/17] KVM: arm64: Skip fixed-feature state flush for protected vCPUs Message-ID: References: <20260831163421.272420-1-fuad.tabba@linux.dev> <20260831163421.272420-6-fuad.tabba@linux.dev> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260831163421.272420-6-fuad.tabba@linux.dev> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260902_080523_179276_5BA5842D X-CRM114-Status: GOOD ( 27.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 31, 2026 at 05:34:09PM +0100, Fuad Tabba wrote: > flush_hyp_vcpu() copies the host's mdcr_el2, TWI/TWE and debug state > into the hyp vCPU on every entry, so for a protected vCPU the host's > trap configuration overrides the one pkvm_vcpu_init_traps() computed > at EL2. Move those copies into the non-protected branch, and sync the > debug state back for non-protected vCPUs only: a protected guest's > debug registers are hypervisor-owned, and it takes the host's TWI/TWE > at vCPU load. MDCR_EL2.TDA traps only the guest's own accesses; it > does not stop the world switch from loading host-supplied breakpoints > and MDSCR_EL1. > > EL2's mdcr_el2 starts from 0, and HPMN == 0 is reserved without > FEAT_HPMN0. Set HPMN to the CPU's event counter count at vCPU load, > the value the host's copy carried; a protected guest's PMU accesses > trap regardless. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 31 +++++++++++++++++++----------- > arch/arm64/kvm/hyp/nvhe/pkvm.c | 2 +- > 2 files changed, 21 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > index ca7122b0bccdd..14e847b122abf 100644 > --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > @@ -231,7 +231,6 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) > u8 esr_ec; > > fpsimd_sve_flush(); > - flush_debug_state(hyp_vcpu); > > /* > * If we deal with a non-protected guest and the state is potentially > @@ -241,7 +240,14 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) > if (!pkvm_hyp_vcpu_is_protected(hyp_vcpu)) { > if (vcpu_get_flag(host_vcpu, PKVM_HOST_STATE_DIRTY)) > flush_hyp_vcpu_state(hyp_vcpu); > + > + hyp_vcpu->vcpu.arch.hcr_el2 &= ~(HCR_TWI | HCR_TWE); > + hyp_vcpu->vcpu.arch.hcr_el2 |= READ_ONCE(host_vcpu->arch.hcr_el2) & > + (HCR_TWI | HCR_TWE); > + > + hyp_vcpu->vcpu.arch.mdcr_el2 = host_vcpu->arch.mdcr_el2; > hyp_vcpu->vcpu.arch.iflags = host_vcpu->arch.iflags; > + flush_debug_state(hyp_vcpu); > } else { > hyp_vcpu->vcpu.arch.ctxt = host_vcpu->arch.ctxt; > } > @@ -249,17 +255,13 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) > /* __hyp_running_vcpu must be NULL in a guest context. */ > hyp_vcpu->vcpu.arch.ctxt.__hyp_running_vcpu = NULL; > > - hyp_vcpu->vcpu.arch.mdcr_el2 = host_vcpu->arch.mdcr_el2; > /* > - * HCR_EL2.VSE is host-owned (a pending virtual SError to inject), not a > - * trap-control bit, so it must flow to the hyp vCPU alongside TWI/TWE > - * for the vSError to be delivered. sync_hyp_vcpu() reflects it back. > + * A host-injected vSError is masked by the guest's own PSTATE.A, so it > + * applies to protected guests too. > */ > - hyp_vcpu->vcpu.arch.hcr_el2 &= ~(HCR_TWI | HCR_TWE | HCR_VSE); > - hyp_vcpu->vcpu.arch.hcr_el2 |= READ_ONCE(host_vcpu->arch.hcr_el2) & > - (HCR_TWI | HCR_TWE | HCR_VSE); > - > - hyp_vcpu->vcpu.arch.vsesr_el2 = host_vcpu->arch.vsesr_el2; > + hyp_vcpu->vcpu.arch.hcr_el2 &= ~HCR_VSE; > + hyp_vcpu->vcpu.arch.hcr_el2 |= READ_ONCE(host_vcpu->arch.hcr_el2) & HCR_VSE; > + hyp_vcpu->vcpu.arch.vsesr_el2 = host_vcpu->arch.vsesr_el2; > > flush_hyp_vgic_state(hyp_vcpu); > > @@ -288,7 +290,8 @@ static void sync_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu, u32 exit_reason) > struct kvm_vcpu *host_vcpu = hyp_vcpu->host_vcpu; > > fpsimd_sve_sync(&hyp_vcpu->vcpu); > - sync_debug_state(hyp_vcpu); > + if (!pkvm_hyp_vcpu_is_protected(hyp_vcpu)) > + sync_debug_state(hyp_vcpu); nit: We can't use the else arm below? > > if (pkvm_hyp_vcpu_is_protected(hyp_vcpu)) { > host_vcpu->arch.ctxt = hyp_vcpu->vcpu.arch.ctxt; > @@ -329,6 +332,12 @@ static void handle___pkvm_vcpu_load(struct kvm_cpu_context *host_ctxt) > /* Propagate WFx trapping flags */ > hyp_vcpu->vcpu.arch.hcr_el2 &= ~(HCR_TWE | HCR_TWI); > hyp_vcpu->vcpu.arch.hcr_el2 |= hcr_el2 & (HCR_TWE | HCR_TWI); > + > + /* HPMN == 0 is reserved without FEAT_HPMN0. */ > + if (system_supports_pmuv3()) > + u64p_replace_bits(&hyp_vcpu->vcpu.arch.mdcr_el2, > + FIELD_GET(ARMV8_PMU_PMCR_N, read_sysreg(pmcr_el0)), > + MDCR_EL2_HPMN); > } else { > memcpy(&hyp_vcpu->vcpu.arch.fgt, hyp_vcpu->host_vcpu->arch.fgt, > sizeof(hyp_vcpu->vcpu.arch.fgt)); > diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c > index 459bd9eb7e4bc..e85f13233da08 100644 > --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c > +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c > @@ -102,7 +102,7 @@ static void pvm_init_traps_mdcr(struct kvm_vcpu *vcpu) > > if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) { > val |= MDCR_EL2_TPM | MDCR_EL2_TPMCR; > - val &= ~(MDCR_EL2_HPME | MDCR_EL2_MTPME | MDCR_EL2_HPMN_MASK); > + val &= ~(MDCR_EL2_HPME | MDCR_EL2_MTPME); > } > > if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, IMP)) > -- > 2.39.5 >