From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18D64C624D3 for ; Wed, 2 Sep 2026 17:23:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XmNQ6WKBMzr8oIBSZDnJlW7h+ZrhoZOuFj83Jzmbsfo=; b=16qbhFU/AHh92pTVzFw/SgVj25 LIfTgLkaxHULyNBNywIm+iMn4IWCjdx47NGRdpUKRVarY1CGvDAIz8oF9JvX6spyYCGJ8q/3R+orc WCmhif10aajVJ6zC8qv5Ra2YDYAx/z76TnKsQ/aMjoRFT3XX8dRdxPMBB05aI2AvprHZSYAgXjncv g34uERm3I/Wvops8Ebz+XOcbZbxMsP/sGwOnBFh2x4tKKPTt+VhlqU8tEw0vlylnDBayoCbpoX8lK q59ujluWO97zbANaPUy6nrVNJzocQBhRi9LovJ6yelyNwiIGA5fHifsIxGL3MWZE5b0H9hGIPBdlg Rar4QFsA==; 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charset=us-ascii Content-Disposition: inline In-Reply-To: <20260822135323.795946-11-ardb+git@google.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Ard, On Sat, Aug 22, 2026 at 03:53:22PM +0200, Ard Biesheuvel wrote: > From: Ard Biesheuvel > > The arm64 module loader has to deal with a couple of corner cases that > may occur when .init.text is placed out of direct branch range of .text: > > - ordinary direct branches from .init.text into .text may require the > use of a PLT entry (i.e., a trampoline aka veneer), which means not > only that additional PLT entries need to be allocated for > cross-section calls, but also that .init.text needs its own PLT > reservation, as the one in .text will be out of range as well; > > - dynamic patching of the ftrace handler into .init.text code needs its > own dedicated trampoline as the one in .text may be too far away. > > - recent compilers may omit BTI veneers for static functions that never > have their address taken, and so additional veneers will need to be > added to .text in case cross-section direct branches from .init.text > require a PLT entry (and therefore a landing pad at the target end). > > This is unfortunate, because it is actually somewhat unusual for .text > and .init.text to be so far away from each other: only when allocating > either of them (but not both) exhausts the 'near' (PLT-less) module > region, the other will be allocated from the spillover region, which is > not in direct branching range, and therefore requires PLT entries for > cross-section calls. > > This series addresses this wart by allocating both of them as a single > chunk, and freeing the .init.text part along with the other init > sections at the appropriate time. This ensures that the two regions will > never require veneers for cross-section calls, allowing the arm64 module > loader to be simplified. > > Ard Biesheuvel (9): > mm: execmem: Add API to split an existing execmem cache allocation > mm: execmem: Allow huge vmappings to be avoided for execmem caches > module: Place MOD_TEXT before MOD_INIT_TEXT in enumeration > module: Allocate MOD_INIT_TEXT from the MOD_TEXT ROX allocation > arm64: mm: Permit permissions changes on huge vmappings > arm64: Enable the execmem ROX cache for module text > arm64: ftrace: Revert "fix unreachable PLT for ftrace_caller ..." > arm64: module: Combine init and core PLT entries again > arm64: ftrace: Simplify PLT handling I can't say I like the idea of tying the single chunk allocation of modules .text and .init.text to the ROX cache. The goal of the cache is to have executable code mapped at higher page table levels. Letting it use base-page mappings completely dismisses it. I'm not against having execmem_split() or something along these lines, but it should work without the ROX cache as well. Another question I had is did you consider splitting the area on free rather than on alloc? In this case it could be execmem_shrink() that immediately frees the .init.text part. > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/module.h | 2 - > arch/arm64/include/asm/module.lds.h | 3 - > arch/arm64/kernel/ftrace.c | 13 +--- > arch/arm64/kernel/module-plts.c | 63 +++++--------------- > arch/arm64/kernel/module.c | 20 +------ > arch/arm64/mm/init.c | 19 +++++- > arch/arm64/mm/pageattr.c | 13 +++- > include/linux/execmem.h | 11 ++++ > include/linux/module.h | 4 +- > kernel/module/main.c | 22 +++++-- > mm/execmem.c | 47 ++++++++++++++- > 12 files changed, 124 insertions(+), 94 deletions(-) > > -- > 2.55.0.860.g4b6b3295ed-goog > -- Sincerely yours, Mike.