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Fri, 4 Sep 2026 18:15:40 -0700 Date: Fri, 4 Sep 2026 18:15:37 -0700 From: Nicolin Chen To: Jonathan Cameron CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 06/13] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Message-ID: References: <9280aea7ae7197eca3f223ef5b998aa25afb29d6.1788222485.git.nicolinc@nvidia.com> <178846311317.1308030.4335813024474016483.b4-review@b4> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <178846311317.1308030.4335813024474016483.b4-review@b4> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|CH3PR12MB9220:EE_ X-MS-Office365-Filtering-Correlation-Id: 53370828-7a1f-4b62-171a-08df0aeb5ab4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|1800799024|82310400026|4143699003|10067099003|11063799006|22082099003|18002099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 94n6ZzD5zG7Pz8E9AwMtF9YQtS62Ky1IZOM1ZodHbFPFIXgCyGCbUw3XnLEn6EqiCURPYF+LOI4s1uGS9BKV0Xkt1q0mOCY7MVyFV5LcQ86NkCEOVg/ZeiXwGTJ0K4lwxYu4q4JVghJIzI19XqAlAHGjQXdIMiPRfge+G1bYpZuVBEXrRPB9geXXEQXyTAlwlcYPq9zVuairAYoKekz5Tuu/Z2WWfNSAYVmKxXSNm0yB3ukWBwrMd+pABQA53jtBDqVX7j8C/W5aZX5vqIoAQXlPEgndSGGMI8JKHGn+ADn4lVXR4ilWMX4uAEQbkGxWMjsINdYRME7otILs84u4bR6FSCJcdHriBZ/H2UQldwyue4Qt+x6+nqPs92VBW7v4ze5XMZ9+4QWZXaTi5wSNmpAItLGD4+/Gbj/Y6EnIlLVv/vGWt8d0AVC4u9XPpZYK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2026 01:16:46.3721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53370828-7a1f-4b62-171a-08df0aeb5ab4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9220 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_181655_137991_5C0F3E6C X-CRM114-Status: GOOD ( 20.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() > > must issue a CMDQ_OP_PRI_RESP back to the SMMU. > > > > A stall event in the EVTQ and a PRI request in the PRIQ both surface to the > > IOPF infrastructure with fault.type == IOMMU_FAULT_PAGE_REQ. SMMUv3 forbids > > the Stall model on PCIe streams (PCIe must use Terminate), and PRI is only > > There are those systems that annoy some because they smell like PCIe > (present PCIe software interfaces) but aren't and use stall mode. However, it > is nonsense to use PRI with stall mode. So, instead I'd just argue that for > stall the fault handling is done synchronously from a device point of > view so a PRI request makes no sense rather htan associating this with > PCIe as such. I changed the paragraph to: A stall event in the EVTQ and a PRI request in the PRIQ both surface to the IOPF infrastructure with fault.type == IOMMU_FAULT_PAGE_REQ. Yet, both two models are alternatives: a stalling master resolves a fault synchronously, holding the transaction until a CMDQ_OP_RESUME, so it has no reason to also issue a page request. A later change refuses PRI on a stall_enabled master, so the two will never co-occur. arm_smmu_page_response() can therefore key on the master state: CMDQ_OP_RESUME for stall_enabled, CMDQ_OP_PRI_RESP for pri_enabled, mapping IOMMU_PAGE_RESP_* to the PRI response codes. > > Co-developed-by: Barak Biber > > Signed-off-by: Barak Biber > > Co-developed-by: Stefan Kaestle > > Signed-off-by: Stefan Kaestle > > Signed-off-by: Malak Marrid > > Signed-off-by: Nicolin Chen > One trivial comment inline. Given I've mostly forgotten how all this > works, this tag might not worth that much! > > Reviewed-by: Jonathan Cameron Your review is helpful! > > + } else if (master->pri_enabled) { > > + enum pri_resp pri_resp; > > + bool ssv; > > + > > + /* PCIe allows only one PRG Response per group */ > > + if (!(evt->fault.prm.flags & > > + IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) > > Go long on that line. It is worth it for readability and it's only 81 > chars. I added a prm and cleaned two: @@ -1061,12 +1061,12 @@ static void arm_smmu_page_response(struct device *dev, struct iopf_fault *evt, } cmd = arm_smmu_make_cmd_resume(sid, resp->grpid, resume_resp); } else if (master->pri_enabled) { + struct iommu_fault_page_request *prm = &evt->fault.prm; enum pri_resp pri_resp; bool ssv; /* PCIe allows only one PRG Response per group */ - if (!(evt->fault.prm.flags & - IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) + if (!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) return; switch (resp->code) { case IOMMU_PAGE_RESP_SUCCESS: @@ -1084,8 +1084,7 @@ static void arm_smmu_page_response(struct device *dev, struct iopf_fault *evt, WARN_ON(true); return; } - ssv = !!(evt->fault.prm.flags & - IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); + ssv = !!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); cmd = arm_smmu_make_cmd_pri_resp(sid, resp->pasid, ssv, resp->grpid, pri_resp); } else { Thanks Nicolin