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Fri, 4 Sep 2026 22:53:29 -0700 Date: Fri, 4 Sep 2026 22:53:27 -0700 From: Nicolin Chen To: Jonathan Cameron CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 13/13] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Message-ID: References: <178846311320.1308030.2192800704181905560.b4-review@b4> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <178846311320.1308030.2192800704181905560.b4-review@b4> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C7:EE_|PH7PR12MB7281:EE_ X-MS-Office365-Filtering-Correlation-Id: eee279c5-9ab0-4715-edaf-08df0b1209d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|376014|7416014|36860700016|10067099003|56012099006|18002099003|22082099003|11063799006|5023799004|4143699003; X-Microsoft-Antispam-Message-Info: e7hor4LnJ7omlsMv2tjdGAa0eTI0sS0Py3uyP/7wvv687a3R+3ntaWl7Ut4D7sf3loy1gW/v1it/fuv0jqHxPFkSJeTTHGhJ9sYM+lGS83rkuB7GMfVbHSmeZHPusphlpGTdqkCqor2N1ARG7KqdmNG3sqpmIDVYW8nCJHfzpNCgFYaWPv4HGrTz41G8VLnp2gX7QoGgGq7KJDBJV5ZWDOqlHKPQwZNaR3DIypJP5EennkNrrKLURp/2po7LMb3VcxMbu9gIKVEzsQCk8pJewadvu4zwRK4x9Juj6EjIWra8bEedPU/7Xip1ztRvOpOe1LOMigaq9WHj3FAx1CNann3+zL6MSYDb4vl2zTpHDIrxOuQ7HycHUbbZ5uyf6xE81KB0It7oiHFlrr3envjLAvJ0h0ESz/jgzOht6v61lfB4h5aZPGh/zYoXKTOCfnfdl5FXIc7LfK6DUmkg+UY27aAzoe7tZR33VSkTZbxVdZr4mAno6rVndU8CT8a4So7gk4hHeUqEZnmWmk4qDxdJavggbOPcarQjcN1HZQ6VOxUO94YHG1qzDFY1/wmDfjmAtFQAuZqXn8T6boQy2AD8vPHrtz99Jpgd+DALjRoDg4ZMRv9STxiC7a/MG0D0SxcVPiDFP2b1OX3X/d6uik4Zl64PcBRKaFrmsT0rOqy9C3/lynxt+mKAHAS4w0xn22SLOJ+8QLy+bH0wTxR94WCh+A== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(23010399003)(376014)(7416014)(36860700016)(10067099003)(56012099006)(18002099003)(22082099003)(11063799006)(5023799004)(4143699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ceQFQTYyt2poL4ujr5ksCmy02MnlC7t62/D4CbcqoWNVIUodCLi3xbXbep+gQ6Qm7U22mdRk1TCOPoqi7gmNMLAXhyNzjkbAAVKcQABdxBb+6DoU0AeGAvrdEntkSYpB8EWOWiaYCtgrPSWthZLbNzUsh96cdYYI0ThPEuQaDUIGo5O/OJKIiioeN96uc6Y8Wrv/UnNsafAHiiEF9Kt1ut15q6lWR9ikfunXC7EHkGH7pAEeLzqpEUxOFDuZhCOulKxdYugyKJISi1LmYGn/Vk6MG4x4I2E9FgG6vVvvWeLhAmGSK716oLxFLPfWKgz8lvzQU22QnA6FnRaIvQv0O9w4SN1+rd5soAYv6DPSqgOQf+V68Em1eA4J1ZEeeFl77ruXmKn4P7+8a4G4mx/Am/tBqjcvnmNAwMIswULCq4m4KEdE/CpqpU98CkHd3prY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2026 05:53:41.2178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eee279c5-9ab0-4715-edaf-08df0b1209d8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7281 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_225351_894408_9A54CA3A X-CRM114-Status: GOOD ( 21.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > SMMUv3 forbids the Stall model on PCIe streams. Refuse to enable PRI on a > > PCIe master that came with stall_enabled, so page_response() can dispatch > > on master state unambiguously. > > As earlier, we have exceptions in tree for Stall mode on PCIe streams > (lets not reopen that fun arguement) so I'd focus this on PRI not > making any sense if stall mode is in use as that has alternative > handling for page faults. Replaced with: A stalling master resolves its faults synchronously, so it has no reason at all to issue a page request. Refuse to enable PRI on such a master, so that page_response() can keep dispatching on the master state unambiguously. > > + /* Same as the eventq drain above, for the hardware priq */ > > + if (master->pri_enabled) { > > + ret |= arm_smmu_drain_queue(smmu, &smmu->priq.q, false); > > + /* Ensure pending requests have reached the IOPF queue */ > > + if (!ret && smmu->priq.q.irq) > > Similar to before, I'd factor out the if (!ret) > Using |= on return values is never particularly nice though safe > as used here. Still I'd use another variable to store that things > timed out already so we are skipping these. OK. Replaced with a "bool timed_out" (in both PATCH-4 and here): @@ void arm_smmu_attach_release(struct arm_smmu_attach_state *state) struct arm_smmu_master_domain *master_domain = state->old_master_domain; struct arm_smmu_master *master = state->master; struct arm_smmu_device *smmu = master->smmu; - int ret = 0; + bool timed_out = false; lockdep_assert_not_held(&arm_smmu_asid_lock); iommu_group_mutex_assert(master->dev); @@ void arm_smmu_attach_release(struct arm_smmu_attach_state *state) * against the next domain. */ if (master->stall_enabled) { - ret = arm_smmu_wait_for_queue_drained(smmu, &smmu->evtq.q, false); + timed_out = arm_smmu_wait_for_queue_drained(smmu, &smmu->evtq.q, + false); /* * Ensure pending events have reached the IOPF queue, unless * the drain timed out: a stuck consumer would also block an * unbounded wait_event() inside the synchronize_irq(). */ - if (!ret) { + if (!timed_out) { if (smmu->evtq.q.irq) synchronize_irq(smmu->evtq.q.irq); /* Pending events might be in the combined_irq handler */ @@ void arm_smmu_attach_release(struct arm_smmu_attach_state *state) /* Same as the eventq drain above, for the hardware priq */ if (master->pri_enabled) { - ret |= arm_smmu_wait_for_queue_drained(smmu, &smmu->priq.q, false); + timed_out |= arm_smmu_wait_for_queue_drained( + smmu, &smmu->priq.q, false); /* Ensure pending requests have reached the IOPF queue */ - if (!ret) { + if (!timed_out) { if (smmu->priq.q.irq) synchronize_irq(smmu->priq.q.irq); /* Pending requests might be in the combined_irq handler */ @@ void arm_smmu_attach_release(struct arm_smmu_attach_state *state) * such work still references. Skip the iopf teardown and * leak master_domain, rather than risk a UAF. */ - if (WARN_ON(ret)) { + if (WARN_ON(timed_out)) { state->old_master_domain = NULL; return; } > > + if (!pci_pri_supported(pdev)) > > + return; > > + > > + /* SMMUv3 forbids the Stall model on PCIe streams */ > > Again, I'd tweak the wording given we have quite a few examples > in tree that do stall mode on PCIe smelling streams. Replaced with: /* A stalling master resolves its faults without any page request */ Thanks Nicolin