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Our SoC (i.MX95) has only 64 SIDs >> total, serving MMC, SD, NET, PCI, DMA, NPU, DSP, DISPLAY and more. >> Some of these are genuinely separate platform devices (distinct DT >> nodes, distinct drivers) that share a SID by hardware design because >> the SID space is exhausted. >> >> That cross-IP case cannot be solved by DT restructuring - the devices >> really are separate. Would you be open to reviewing the shared-SID >> SMMU support (patches 1-4) on that basis, independent of the DMA >> channel question? > >I think you should revise your commit message/cover letter to focus on >something that is not a DT abuse and try again Yes. I will prepare RFC V2 with revised cover letter. > >IIRC Robin said the SID aliasing was a PITA on SMMUv2 so it >really needs to have a strong reason. Not like sever/data center chips, i.MX95 does not the advanced features, so in [PATCH RFC 4/4], those advanced features are marked as not supported. In the chip internal bus, there are only 6 bits are used to carry SID on the bus, so limited SIDs. Hope we could move forward to support just simple SID sharing between platform devices without advancing features. Thanks, Peng > >Jason > >