From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAB8EC79FB7 for ; Wed, 9 Sep 2026 15:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/mqbOi63kUAsHZ0zibDAGgq9MP2n2OnK+z4SkjemtbY=; b=g0UhqGSerGd3QzmareJ+tnjzqW Qiggk0sM6i64Y6uck1e9iXMSAG92mIgWBeaC1lG+umyu+lF2AyxSbHiW0andhHu5Tk3G5PckvtUxg hVS6Z1v5q46sBR3mUFK1Qjo5B84AiC6QNH2KpjzTaQQpBAesPCee4E9jKLsTZpivHWeDMq9h5282X WdVq40UJ9Vq6lYM86uKvAyma1TMIkjNlxvGZlsHQZIMhy7VhIYrXgyc5YRmx4SDVaP+kjfw7wEtQ0 qsnPBocan1FhsNSZSPlBo1OXe5LTdCAOtvUPYPajTpEoh/v6LYfqOksmtilJQdE6sVngT1uwDk4cD iiJb5Tdg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x4KJf-0000000CBMD-3JcS; Wed, 09 Sep 2026 15:34:27 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1x4KJe-0000000CBLq-2JV6 for linux-arm-kernel@lists.infradead.org; Wed, 09 Sep 2026 15:34:26 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 389FD41443; Wed, 9 Sep 2026 15:34:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B9291F00A3A; Wed, 9 Sep 2026 15:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788968066; bh=/mqbOi63kUAsHZ0zibDAGgq9MP2n2OnK+z4SkjemtbY=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=MpyBAmy9ewejgBOq+OB5P5O7yETpZk5Hf7Q+jwseySYEfIgEkCm2kLCZMQ/y6taiG eYYFvYPBOQcrWusC2JU5EwpDLxm/PGg6gnMFb+DuOmWUqbr/PcCby8AOean7+QbjGD o5Fr5RRyjgOzzznaIyHBoPrhZBxcJm4APuYa87s/U9Bs/t5H4PBtaC4xvLa1QB2zdL 0FfTdPtteaC1WKR2yXdMaQmKcuOtGcTHuoiVpM9CpBrI2hQk8fg8ovWxtiXOq8yawt l75qnotc/R3J42VSMF1TGXFMAM6rjUYu8YaznJlNMRlCPHicVz86BGsNtRAXlTwmvb GWyAtNcbsFWow== Date: Wed, 9 Sep 2026 16:34:18 +0100 From: Will Deacon To: Andrea Righi Cc: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot , Catalin Marinas , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Mark Rutland , Christian Loehle , Shrikanth Hegde , Phil Auld , Breno Leitao , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Message-ID: References: <20260909062649.469633-1-arighi@nvidia.com> <20260909062649.469633-2-arighi@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260909062649.469633-2-arighi@nvidia.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote: > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index d28438f8b83f1..e5a7a4b2e3844 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -19,6 +19,8 @@ > #include > #include > #include > +#include > +#include > #include > > #include > @@ -44,6 +46,55 @@ > static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) = 1UL << (2 * SCHED_CAPACITY_SHIFT); > static cpumask_var_t amu_fie_cpus; > > +/* > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in > + * two-thread active mode, with resources partitioned between the PEs. > + * > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource > + * mode. Firmware does not currently describe this preference, so detect > + * Olympus by MIDR until a firmware interface is available. > + */ Fix the firmware? If we add this MIDR kludge, I guarantee that it will never be fixed. Will