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The control region > manages shared resources such as firmware memory, while each interface > region has its own MMIO range and interrupt. > > The control region and each interface region are distinct DMA requesters > and can be associated with separate IOMMU stream IDs. Represent the > control region as the parent node and the interface register regions as > child nodes to describe these resources. > > Signed-off-by: Nas Chung > --- Reviewed-by: Frank Li > .../bindings/media/nxp,imx95-vpu.yaml | 162 ++++++++++++++++++ > MAINTAINERS | 7 + > 2 files changed, 169 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml > new file mode 100644 > index 000000000000..aa7dd8838af0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml > @@ -0,0 +1,162 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/nxp,imx95-vpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Chips&Media Wave6 Series multi-standard codec IP on NXP i.MX SoCs > + > +maintainers: > + - Nas Chung > + - Jackson Lee > + > +description: > + The Chips&Media Wave6 codec IP is a multi-standard video encoder/decoder. > + On NXP i.MX SoCs, the Wave6 codec IP exposes one control register region and > + four interface register regions for a shared video processing engine. > + The parent node describes the control region, which has its own MMIO range and > + manages shared resources such as firmware memory. The child nodes describe the > + interface register regions. Each interface region has its own MMIO range and > + interrupt. > + The control region and the interface regions are distinct DMA requesters. > + The control region and each interface region can be associated with separate > + IOMMU stream IDs, allowing DMA isolation between them. > + > +properties: > + compatible: > + enum: > + - nxp,imx95-vpu > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: VPU core clock > + - description: VPU associated block clock > + > + clock-names: > + items: > + - const: core > + - const: vpublk > + > + power-domains: > + items: > + - description: Main VPU power domain > + - description: Performance power domain > + > + power-domain-names: > + items: > + - const: vpu > + - const: perf > + > + memory-region: > + maxItems: 1 > + > + sram: > + maxItems: 1 > + description: > + Used to store reference data, reducing DMA memory bandwidth. > + > + iommus: > + maxItems: 1 > + > + "#cooling-cells": > + const: 2 > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +patternProperties: > + "^interface@[0-9a-f]+$": > + type: object > + description: > + An interface register region within the Chips&Media Wave6 codec IP. > + Each region has its own MMIO range and interrupt and can be associated > + with a separate IOMMU stream ID for DMA isolation. > + additionalProperties: false > + > + properties: > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + required: > + - reg > + - interrupts > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - power-domain-names > + - memory-region > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + video-codec@4c4c0000 { > + compatible = "nxp,imx95-vpu"; > + reg = <0x0 0x4c4c0000 0x0 0x10000>; > + clocks = <&scmi_clk 115>, > + <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>; > + clock-names = "core", "vpublk"; > + power-domains = <&scmi_devpd 21>, > + <&scmi_perf 10>; > + power-domain-names = "vpu", "perf"; > + memory-region = <&vpu_boot>; > + sram = <&sram1>; > + iommus = <&smmu 0x32>; > + #cooling-cells = <2>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + interface@4c480000 { > + reg = <0x0 0x4c480000 0x0 0x10000>; > + interrupts = ; > + iommus = <&smmu 0x33>; > + }; > + > + interface@4c490000 { > + reg = <0x0 0x4c490000 0x0 0x10000>; > + interrupts = ; > + iommus = <&smmu 0x34>; > + }; > + > + interface@4c4a0000 { > + reg = <0x0 0x4c4a0000 0x0 0x10000>; > + interrupts = ; > + iommus = <&smmu 0x35>; > + }; > + > + interface@4c4b0000 { > + reg = <0x0 0x4c4b0000 0x0 0x10000>; > + interrupts = ; > + iommus = <&smmu 0x36>; > + }; > + }; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index 8d9648737e92..7387a11facbe 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -29233,6 +29233,13 @@ S: Maintained > F: Documentation/devicetree/bindings/media/cnm,wave521c.yaml > F: drivers/media/platform/chips-media/wave5/ > > +WAVE6 VPU CODEC DRIVER > +M: Nas Chung > +M: Jackson Lee > +L: linux-media@vger.kernel.org > +S: Maintained > +F: Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml > + > WHISKEYCOVE PMIC GPIO DRIVER > M: Kuppuswamy Sathyanarayanan > L: linux-gpio@vger.kernel.org > -- > 2.31.1 >