Re: [PATCH 1/9] ARM: dts: imx6ul-kontron-bl-common: Replace UART3 with DIP switch GPIOs

[Frank Li <Frank.li@oss.nxp.com>]

On Thu, Sep 10, 2026 at 09:05:14AM +0200, Frieder Schrempf wrote:
> On 09.09.26 20:45, Frank Li wrote:
> > On Tue, Sep 08, 2026 at 03:51:48PM +0200, Frieder Schrempf wrote:
> >> From: Eberhard Stoll <eberhard.stoll@kontron.de>
> >>
> >> The latest board revision has DIP switches and lacks UART3 instead.
> >> As the old revision has long been deprecated and not maintained
> >> anymore, drop the support and reflect the current state of the
> >> hardware. As the old revision hasn't been widely used, UART3 was
> >> only available through an obscure extension connector and we have
> >> carried this patch downstream for years, no users are expected to
> >> be affected by this change.
> >
> > Remove "we have carried this patch downstream for years".
>
> Ok.
>
> >
> >>
> >> Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de>
> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> >> ---
> >>  .../boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi  | 21 +++++----------------
> >>  1 file changed, 5 insertions(+), 16 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
> >> index f4c45e964daf..a71669bef7d4 100644
> >> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
> >> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi
> >> @@ -172,13 +172,6 @@ &uart2 {
> >>  	status = "okay";
> >>  };
> >>
> >> -&uart3 {
> >> -	pinctrl-names = "default";
> >> -	pinctrl-0 = <&pinctrl_uart3>;
> >> -	uart-has-rtscts;
> >> -	status = "okay";
> >> -};
> >> -
> >>  &uart4 {
> >>  	pinctrl-names = "default";
> >>  	pinctrl-0 = <&pinctrl_uart4>;
> >> @@ -283,6 +276,11 @@ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0	/* DOUT1 */
> >>  			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* DIN1 */
> >>  			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x1b0b0	/* DOUT2 */
> >>  			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0	/* DIN2 */
> >> +
> >> +			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x1b0b0	/* CAN_ADR0 (DIP sw 1) */
> >> +			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* CAN_ADR1 (DIP sw 2) */
> >> +			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x1b0b0	/* CAN_ADR2 (DIP sw 3) */
> >> +			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x1b0b0	/* CAN_ADR3 (DIP sw 4) */
> >
> > supposed header overlay or real user should set it. otherwise, the real
> > user set it will be failure because pin conflict.
>
> Sorry, I can't figure out what you are suggesting here.

Please forget it.  I mess up.

Frank
>
> >
> > Frank
> >>  		>;
> >>  	};
> >>
> >> @@ -334,15 +332,6 @@ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS	0x1b0b1
> >>  		>;
> >>  	};
> >>
> >> -	pinctrl_uart3: uart3grp {
> >> -		fsl,pins = <
> >> -			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
> >> -			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
> >> -			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b1
> >> -			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
> >> -		>;
> >> -	};
> >> -
> >>  	pinctrl_uart4: uart4grp {
> >>  		fsl,pins = <
> >>  			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
> >>
> >> --
> >> 2.55.0
> >>
> >>
>