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Tue, 15 Sep 2026 12:16:48 +0000 Date: Tue, 15 Sep 2026 05:16:42 -0700 From: Breno Leitao To: "Kiryl Shutsemau (Meta)" Cc: Will Deacon , Robin Murphy , Joerg Roedel , Nicolin Chen , Jason Gunthorpe , Pranjal Shrivastava , Mostafa Saleh , Thierry Reding , Krishna Reddy , Jonathan Hunter , Kyle McMartin , Usama Arif , kernel-team@meta.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 1/2] iommu/arm-smmu-v3: Add a cmdq_max_n_shift module parameter Message-ID: References: <20260909095228.2174031-1-kas@kernel.org> <20260909095228.2174031-2-kas@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260909095228.2174031-2-kas@kernel.org> X-Debian-User: leitao X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_131704_004518_94F95A13 X-CRM114-Status: GOOD ( 14.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 09, 2026 at 10:52:27AM +0100, Kiryl Shutsemau (Meta) wrote: > The command queue depth comes straight from the maximum the hardware > advertises in IDR1, which reaches megabytes of coherent DMA per queue. > A system with several SMMUv3 instances pays that per instance, and the > Tegra241 CMDQV pays it again for every VCMDQ it preallocates. Thanks. I've seen this issue while investigating another SMMU issue[1]. Thanks for fixing it. Link: https://lore.kernel.org/all/20260911-smmu_fix_aws-v1-0-75870bf9655b@debian.org/ [1] > Queue depth only bounds how many commands may be in flight before a sync. > A machine driving a handful of devices, or one with a tight memory budget, > has no use for the maximum, and no way to say so. > > Add cmdq_max_n_shift, a cap on the depth given as the log2 of the entry > count, the form the hardware itself takes in the LOG2SIZE field of > CMDQ_BASE. Decide the depth in arm_smmu_cmdq_max_n_shift(), which caps the > IDR1 value for natural alignment and then applies the parameter, so the > queue is allocated at the requested size. The Tegra241 CMDQV sizes its > VCMDQs from IDR1 itself, so route that through the same helper. > > Floor the request at one page worth of entries. Without the floor, a small > request trips the CMDQ_BATCH_ENTRIES check in arm_smmu_device_hw_probe() > and the SMMU fails to probe. The floor also costs nothing: coherent DMA is > page granular, so a shallower queue occupies the same memory as one that > fills the page. > > Assisted-by: LLM > Signed-off-by: Kiryl Shutsemau (Meta) Reviewed-by: Breno Leitao