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The upper bits, above >> bit 35, of the ARADDR and ACADDR buses within the Arm A53 subsystem >> have been incorrectly connected. This causes some TLBI and IC >> maintenance operations exchanged between the A53 and A72 core clusters >> to be corrupted. >> >> The workaround requires: >> >> - Downgrading targeted TLBI operations to broadcast-all variants. >> Instead of patching the low-level __TLBI_1 macro (which interferes >> with the REPEAT_TLBI workaround and causes excessive over- >> invalidation), redirect high-level TLB flush functions >> (flush_tlb_mm, __do_flush_tlb_range, flush_tlb_kernel_range, >> __flush_tlb_kernel_pgtable) to use VMALLE1IS via static key checks. >> >> - Upgrading IC IVAU to IC IALLUIS for both kernel (via ALTERNATIVE in >> invalidate_icache_by_line) and EL0 userspace (via trap-and-upgrade >> in user_cache_maint_handler with SCTLR_EL1.UCI=0). >> >> - Disabling KVM since correct TLB maintenance cannot be guaranteed >> for guests. >> >> - No need to touch SMMU Broadcast TLB Maintenance (BTM) since i.MX8QM >> does not support broadcast TLB. >> >> SoC detection uses devicetree compatible string "fsl,imx8qm" or >> "fsl,imx8qp" since the boot CPU MIDR_EL1 (0x410fd034) and AIDR_EL1 (0) >> are not unique to this SoC. >> >> [1] https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf > >Hi Peng, > >I tested this on our HW and the random crashes that occured when both >the A72 and A53 clusters were enabled no longer happen. > >Tested-by: Franz Schnyder # Toradex Apalis iMX8QM Hi Franz, Thanks a lot for testing this patch. Thanks, Peng > >Thanks > >Franz > >