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X-CSE-ConnectionGUID: fcRclNrkQX2FvcmV2Pm+Dg== X-CSE-MsgGUID: SalNyZTLTJKI3D8V0sdgcg== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="93798678" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="93798678" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 03:23:54 -0700 X-CSE-ConnectionGUID: zZTsqc9USHyL5sqH2UfPDg== X-CSE-MsgGUID: 8JRWbhnbR4S5o23MCxAirA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="311581967" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.244.145]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 03:23:48 -0700 Date: Wed, 16 Sep 2026 13:23:45 +0300 From: Andy Shevchenko To: Linus Walleij Cc: Bartosz Golaszewski , soc@lists.linux.dev, longzhao@ambarella.com, Long Zhao via B4 Relay , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Greg Kroah-Hartman , Jiri Slaby , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Message-ID: References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260916_032355_950423_612254CD X-CRM114-Status: GOOD ( 20.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote: > On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski wrote: > > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay > > said: > > > This series adds minimal Ambarella CV75 support for early bring-up with > > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > > > MAINTAINERS. > > > > > > This is a single unified series. Please apply via the SoC > > > tree; subsystem maintainers are Cc'd for their pieces. > > > > I would prefer to take the GPIO regmap bits through the GPIO tree and provide > > an immutable branch to the SoC tree as it has potential for conflicts that > > early into the cycle. > > Queue them up and send us the IB if you think they are ready! > > Long can probably send a PR based on that IB for the rest to the > SoC tree, a bit tricksy but it works. I'm still unsure why we can't use IRQ facility from gpio-regmap. Can you have a look there? With that being said, I'm not sure that the patch that exposing gpio_chip from gpio-regmap is justified. The whole GPIO rework needs a bit more routine work (resplitting, refactoring, et cetera), so later we may see clearer what's going on. -- With Best Regards, Andy Shevchenko