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X-CSE-ConnectionGUID: /c49hALGTUKFDsfWK4CEPg== X-CSE-MsgGUID: 7U52kNHwRc+jVcvTsscE1A== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="93653722" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="93653722" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 08:20:50 -0700 X-CSE-ConnectionGUID: JwexR3oJQzatmu4g5LEWDA== X-CSE-MsgGUID: vFlYH9tyRkangFMS75Q85w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="296853472" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.244.145]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 08:20:43 -0700 Date: Wed, 16 Sep 2026 18:20:40 +0300 From: Andy Shevchenko To: zl020895 Cc: Linus Walleij , Bartosz Golaszewski , soc@lists.linux.dev, longzhao@ambarella.com, Long Zhao via B4 Relay , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Greg Kroah-Hartman , Jiri Slaby , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Catalin Marinas , Will Deacon , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , linux-arm-kernel@lists.infradead.org Subject: Re: Re: [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Message-ID: References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> <23d61058.962b.1a0a9e0b355.Coremail.zl020895@163.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <23d61058.962b.1a0a9e0b355.Coremail.zl020895@163.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260916_082050_178402_00B58CDE X-CRM114-Status: GOOD ( 29.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 16, 2026 at 07:01:10PM +0800, zl020895 wrote: > ACK: GPIO bits through the GPIO tree, then an IB for the SoC tree. > I will keep a unified series for now. > > regmap-irq cannot do PL061 type (IS/IBE/IEV, both-edge) plus the > AMBA chained demux. > > Two options for v8 — Andy, which do you prefer? > 1) Convert PL061 MMIO to regmap only. Keep the existing gpio_chip > and irqchip/girq (double-write stays in the driver). Ambarella > layout can be a follow-up on that. No gpio-regmap yet. > > 2) After (1), also move get/set/direction to gpio-regmap. IRQ > would stay a custom PL061 irqchip (not regmap-irq). I am not > sure we can avoid a way to get the gpio_chip for > gpiochip_*_irq() / the chained handler. > > I am leaning to (1) for v8. I would prefer to see (2) and then we can discuss to roll-back if it looks not good enough. Either way your PM runtime support for gpio-regmap is a good change. > 在 2026-09-16 18:23:45，"Andy Shevchenko" 写道： > >On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote: > >> On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski wrote: > >> > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay > >> > said: > >> > > This series adds minimal Ambarella CV75 support for early bring-up with > >> > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > >> > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > >> > > MAINTAINERS. > >> > > > >> > > This is a single unified series. Please apply via the SoC > >> > > tree; subsystem maintainers are Cc'd for their pieces. > >> > > >> > I would prefer to take the GPIO regmap bits through the GPIO tree and provide > >> > an immutable branch to the SoC tree as it has potential for conflicts that > >> > early into the cycle. > >> > >> Queue them up and send us the IB if you think they are ready! > >> > >> Long can probably send a PR based on that IB for the rest to the > >> SoC tree, a bit tricksy but it works. > > > >I'm still unsure why we can't use IRQ facility from gpio-regmap. > >Can you have a look there? > > > >With that being said, I'm not sure that the patch that exposing gpio_chip > >from gpio-regmap is justified. > > > >The whole GPIO rework needs a bit more routine work (resplitting, refactoring, > >et cetera), so later we may see clearer what's going on. -- With Best Regards, Andy Shevchenko