From: Mark Rutland <mark.rutland@arm.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
Randy Dunlap <rdunlap@infradead.org>,
Robin Murphy <robin.murphy@arm.com>,
Shuah Khan <skhan@linuxfoundation.org>,
Will Deacon <will@kernel.org>,
David Matlack <dmatlack@google.com>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Nicolin Chen <nicolinc@nvidia.com>,
Pasha Tatashin <pasha.tatashin@soleen.com>,
patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
Samiullah Khawaja <skhawaja@google.com>,
Mostafa Saleh <smostafa@google.com>,
stable@vger.kernel.org,
Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
Subject: Re: [PATCH v6 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA
Date: Thu, 17 Sep 2026 10:24:08 +0100 [thread overview]
Message-ID: <aquxuBnh6pdxu4-8@J2N7QTR9R3> (raw)
In-Reply-To: <1-v6-9cd17417d355+281836-smmu_tlbi_jgg@nvidia.com>
Hi Jason,
Nit on terminology below.
On Wed, Sep 16, 2026 at 09:27:42PM -0300, Jason Gunthorpe wrote:
> The erratum (MMU-700: #3777127, S3: #3673557) deals with under
> invalidation of a CONT PTE grouping in the SMMU. The recommended work
> around is to use a Range Invalidate (RIL) that spans the entire CONT. The
> only user of CONT in the kernel right now is through SVA sharing a CPU
> page table that contains a CONT created by the mm.
As someone familiar with VMSA, I've never seen "RIL" used to describe a
range invalidate and I think using that in the code below is confusing.
I *think* "RIL" has come from "SMMUv3.2-RIL", which is the SMMU feature
for Range Invalidate *and* Level hint, where "RI" is Range Invalidate,
and "L" is Level.
Can we please spell that out as "range invalidate" or "range op"
(matching the arm64 architecture code) rather than "RIL"?
That'll be easier to follow, especially as nothing in the code mentions
what "RIL" means -- that's only mentioned in this commit message.
Mark.
next prev parent reply other threads:[~2026-09-17 9:24 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 0:27 [PATCH v6 0/9] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA Jason Gunthorpe
2026-09-17 9:24 ` Mark Rutland [this message]
2026-09-17 13:16 ` Jason Gunthorpe
2026-09-17 13:44 ` Will Deacon
2026-09-17 13:47 ` Jason Gunthorpe
2026-09-17 13:56 ` Mark Rutland
2026-09-17 13:52 ` Mark Rutland
2026-09-17 0:27 ` [PATCH v6 2/9] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 3/9] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 4/9] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 5/9] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 6/9] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 7/9] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 8/9] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-09-17 0:27 ` [PATCH v6 9/9] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-09-17 2:43 ` [PATCH v6 0/9] Organize the SMMUv3 invalidation flow so iommupt can use it Nicolin Chen
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