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Wed, 30 Sep 2026 12:02:32 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 12:02:30 -0700 Date: Wed, 30 Sep 2026 12:02:28 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , , Thomas Gleixner , Radu Rendec , Bjorn Helgaas , , , "Greg Kroah-Hartman" , , "Danilo Krummrich" , Subject: Re: [PATCH v11 12/16] iommu/tegra241-cmdqv: Add a helper to quiesce VCMDQs Message-ID: References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-13-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260929034510.2023173-13-praan@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|PH7PR12MB5997:EE_ X-MS-Office365-Filtering-Correlation-Id: 23a9c063-b919-4ec9-f70d-08df1f257459 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|23010399003|82310400026|1800799024|7416014|4143699003|10067099003|3023799007|11063799006|56012099006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0c9z9t7wP+/qH+SsS6U7VXeCPz4IcxJ0p9zkSkhaKilkNJZM3Zg7aXKHrCw4n7Pmof+yExo4KX+OYIYUep3mFPFqTppH99yCrjN9qDj/Gvych3lOVylSe6EeAsfPsKllqVCpxiHn6QqAnp7SlUtiLJV1PfxpQM9ozY3+YKbSmX1+ZXNFMw/IJmU7B1g3KPdhBArd18B6qqUoigcFN4nODyux67ku8oIPViLr91K95b6SAaRvOVO9fxqqXtOGrMqkhaQZtHv+O/ETuNHR6EOhiXMzK1CRBPloKrVKGGjZF8EeJxPjDuBtReKD5vSOjAk85KzkVwO61iLBy0VdTKqZg/8HkWgLojUjtv3ad7cU7CKf+djDqX/SPvFokfqZUNfyaLKBMaTg5HpzUFmk646PcDQE1rt4MUKeT8Su0SIc6b+BgXGGcbdwst6yLHeoCpXl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 19:03:03.4691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23a9c063-b919-4ec9-f70d-08df1f257459 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5997 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260930_120310_736823_9CBC85ED X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 29, 2026 at 03:45:06AM +0000, Pranjal Shrivastava wrote: > The tegra241-cmdqv driver supports vCMDQs which need to be quiesced using > the STOP_FLAG. The current driver implementation only uses VINTF0 for > vCMDQs owned by the kernel which need to be stopped. Add a helper that > sets the CMDQ_PROD_STOP_FLAG on these vCMDQs. > > Consolidate this logic by renaming the implementation hook to > quiesce_and_drain_queues and ensuring that the tegra241-cmdqv driver > gates all active local virtual queues before starting the drain loop. > Additionally, clear the STOP_FLAG in tegra241_vcmdq_hw_init() as a part > of tegra241_cmdqv_hw_reset(). This whole suspend routine is missing the CMDQV flags. vintf->enabled and vcmdq->enabled must be cleared when the system does suspend, via tegra241_vintf_hw_deinit(vintf0). So, instead of quiesce_and_drain_queues, perhaps we need a suspend callback that: - set stop flags to all lvcmdqs - wait for all lvcmdqs being drained - hw_deinit vintf0 and its lvcmdqs > @@ -566,7 +632,6 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) > > /* Configure and enable VCMDQ */ > writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); > - > /* > * HW Registers reset to 0 when power-cycled. Restore them from their > * SW copies to prevent executing stale/ghost commands after resume. Meaningless line removal. Nicolin