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d="scan'208";a="95396583" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2026 00:20:32 -0700 X-CSE-ConnectionGUID: R8cZksT4SGyr7eFGfnLaAQ== X-CSE-MsgGUID: bpltgbzmR/6D/vwvT0LK8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,134,1787036400"; d="scan'208";a="302171307" Received: from abityuts-desk1.ger.corp.intel.com (HELO localhost) ([10.245.244.27]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2026 00:20:30 -0700 Date: Thu, 1 Oct 2026 10:20:27 +0300 From: Andy Shevchenko To: Shih-Yuan Lee Cc: Mark Brown , Mika Westerberg , Lukas Wunner , Daniel Mack , Haojian Zhuang , Robert Jarzmik , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v17 5/6] spi: pxa2xx-pci: restore LPSS private register state across S3 resume Message-ID: References: <20260930160629.1822-1-fourdollars@debian.org> <20260930160629.1822-6-fourdollars@debian.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260930160629.1822-6-fourdollars@debian.org> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_082039_432189_352D7FF1 X-CRM114-Status: GOOD ( 19.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 01, 2026 at 12:06:28AM +0800, Shih-Yuan Lee wrote: > On platforms where Intel LPSS SPI is enumerated as a bare PCI device > (such as the Apple MacBook8,1 on Lynxpoint-LP), the LPSS power island > loses power during system sleep and powers up with the controller held > in reset. Because the device lacks ACPI companion objects or MFD > binding, neither drivers/acpi/x86/lpss.c nor drivers/mfd/intel-lpss.c > restore the private register context across S3 resume. > > This causes memory-mapped I/O reads on resume to return ~0, resulting > in PCIe Completion Timeouts, missing interrupts, and dead > keyboard/touchpad. > > Restore LPSS private registers and deassert functional, APB, and iDMA > resets in the PCI glue layer: > 1. In suspend, quiesce the controller queue via spi_controller_suspend() > so no transfers remain in flight and chip select is deasserted. > Then save the LPSS private registers (LPSS_PRIV_REG_COUNT 9 covering > up to offset 0x20 including reg_cs_ctrl at 0x18). Ensure the clock is > active for reading MMIO registers using pm_runtime_resume_and_get(), > balanced by pm_runtime_put_noidle(), before calling > pm_runtime_force_suspend(). > 2. In resume, restore LPSS private registers and deassert functional, > APB, and iDMA resets via pxa2xx_spi_pci_lpss_restore_ctx() before > calling pm_runtime_force_resume(). Because the controller clock > remains gated (clk_enabled is false) during this restoration, any > interrupt arriving on a shared line bails out early in ssp_int() > without accessing registers on a controller held in reset. Once > resets are deasserted and private registers are restored, call > pm_runtime_force_resume() to enable the clock and mark the device > active, and restart the queue with spi_controller_resume(). > 3. In probe, call pci_d3cold_disable() for Lynxpoint-LP (is_lpt) to > ensure the PCI device cannot enter D3cold during runtime PM, > guaranteeing that LPSS private registers are retained during S0 idle > periods and only require restoration across S3 system sleep. Set > DPM_FLAG_NO_DIRECT_COMPLETE to prevent PCI subsystem direct-complete > bypassing system sleep callbacks. > 4. Scope LPSS context restoration specifically to Lynxpoint-LP > (PCI_DEVICE_ID_INTEL_LPT*) devices to avoid perturbing other LPSS > PCI platforms (BYT, BSW) or non-LPSS platforms. > > Export lpss_ssp_setup() and core runtime PM ops so the PCI glue layer > can invoke them around private register restoration. No, as I told earlier please find a way how to not add a code duplication. > Assisted-by: Antigravity:gemini-3.8-flash sparse Assisted-by: LLM -- With Best Regards, Andy Shevchenko