From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53F6ECA5FD9 for ; Fri, 2 Oct 2026 07:41:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VqhHVgP+5BEP2wedjviave4vYLoLXvJXwbeTOEQerOU=; b=nZNxPDneofiNFWUpXJo9CQnoXF r64YaLpNZei0TqCFbVwfuk4irqBW7ylvo9Wf04iU9iJ9akf91SJFOqSwYfYhT3vRpKCPRhsl23GH5 Xb1GVHjHorHru9GrfGFvDPgorx7Nqs9atq+1dlGuv82VV0viOZcnj5IXalQ47rDjDop1xlQ/JlePa OLj9IZgGqSeIfeeh2B4pcv4XpaHLcr8YfIxvWSNRY5Nx8c+NR654DzoeduUInBEmUJ5UE06BMFhPR B5i3EJKnQF9FWpOSie7mLwxfK/Rnc89Ect3N+xnl7uz46yQFE+lT3PcK602fw0WmYIL4e8Bu+DecZ nrUcj14g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCXtg-0000000As79-2ljo; Fri, 02 Oct 2026 07:41:36 +0000 Received: from mgamail.intel.com ([198.175.65.17]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCXtf-0000000As6S-0piG for linux-arm-kernel@lists.infradead.org; Fri, 02 Oct 2026 07:41:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790926895; x=1822462895; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=C/kv6wcM0+ohmmG/4GwabO9Kw2Wi6mMW0E4cJ8FNzUM=; b=O0Aijr7T6JyIud/Ad9DCQ+/66RwaG1KTHRT4wcJZlQHrBWx3g+D0I4NC UwwGqjxzkWfJVKN3CVbp+MUv+M+GBZE0+dbS907QYoiaF9BuaSJq1yRZV wQpo4zLmlD64Whf6Lz0UH/Jed+bRm5Ymqe1eLyCOEHJJ/iUVjGsbjx51V rdkqvUMcVQIPeqDU3xaRgzKQZ3xLgUvD3pQwgBmh2MrBwSO5awORFKAWH f3F7AKMsD2CU8Oo4YWgLQtpvE3vBtyEUtPa5mKFo/LwAOeq60JRgluCXS smUEKSImKT0UANKH1bLfN/tnHjAZSlBtGqyViW49UxmDhikVRfYggQybn Q==; X-CSE-ConnectionGUID: xXXCh1gMTLSAb+uTxA1bbA== X-CSE-MsgGUID: bJeVpfQYQjqwUm6swyc8/A== X-IronPort-AV: E=McAfee;i="6800,10657,11922"; a="90723489" X-IronPort-AV: E=Sophos;i="6.27,136,1787036400"; d="scan'208";a="90723489" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2026 00:41:34 -0700 X-CSE-ConnectionGUID: Wr8ybAupREydeJzXx1ceWw== X-CSE-MsgGUID: VX/xtgwiQPOs9W6Qu5jQYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,136,1787036400"; d="scan'208";a="280935559" Received: from conormcd-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.244.188]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2026 00:41:29 -0700 Date: Fri, 2 Oct 2026 10:41:25 +0300 From: Andy Shevchenko To: longzhao@ambarella.com Cc: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v9 07/15] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Message-ID: References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> <20261001-cv75-v5-v9-7-486cc289a4b8@ambarella.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261001-cv75-v5-v9-7-486cc289a4b8@ambarella.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261002_004135_276569_7411904A X-CRM114-Status: GOOD ( 18.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 01, 2026 at 08:40:56PM +0800, Long Zhao via B4 Relay wrote: > Some controllers ignore output writes while a line is still an input. > Add a behaviour flag so the output value is written after the direction > change. This is a legacy quirk. New hardware must not use it. A nit-pick below. In general looks good to me. Reviewed-by: Andy Shevchenko ... > struct gpio_regmap { > unsigned int reg_clr_base; > unsigned int reg_dir_in_base; > unsigned int reg_dir_out_base; > + unsigned long quirks; I think I have told at some point that this location is not the best, I woul put it... > unsigned long *fixed_direction_mask; > unsigned long *fixed_direction_output; ...here, after the group of the direction related offsets and masks. > - gpio_regmap_set(chip, offset, value); > + if (!(gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR)) > + gpio_regmap_set(chip, offset, value); > > - return gpio_regmap_set_direction(chip, offset, true); > + ret = gpio_regmap_set_direction(chip, offset, true); > + if (ret) > + return ret; > + > + if (gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR) > + gpio_regmap_set(chip, offset, value); > + > + return 0; > } ... > /** > * struct gpio_regmap_config - Description of a generic regmap gpio_chip. > * @parent: The parent device > * @ngpio: (Optional) Number of GPIOs > * @names: (Optional) Array of names for gpios > + * @quirks: (Optional) Behaviour flags, OR of GPIO_REGMAP_QUIRK_*. > * @reg_dat_base: (Optional) (in) register base address > * @reg_set_base: (Optional) set register base address > * @reg_clr_base: (Optional) clear register base address > int ngpio; > const char *const *names; > > + /* Regmap GPIO behaviour flags */ > + unsigned long quirks; > + > unsigned int reg_dat_base; > unsigned int reg_set_base; > unsigned int reg_clr_base; I would follow the same location as it's in the above struct, id est after unsigned long *fixed_direction_output; member. -- With Best Regards, Andy Shevchenko