Hello Mani, On Sat, Sep 26, 2026 at 09:54:56AM +0200, Manivannan Sadhasivam wrote: > On Tue, Sep 15, 2026 at 05:32:48PM +0200, Sebastian Reichel wrote: > > To resolve issues with running into permanent "cmn ana lcpll lock > > timeout" errors after a few device replugs, add support for reset > > notifications, which will be handled by the DWC3 driver to gracefully > > handle the PHY being disabled. This avoids corrupting the controller's > > internal state and the PIPE interface between the USB3 controller and > > the PHY, thus fixing the issue. > > > > Tested-by: Igor Paunovic # Orange Pi 5 Plus > > Signed-off-by: Sebastian Reichel > > --- > > drivers/phy/rockchip/phy-rockchip-usbdp.c | 19 +++++++++++++++++-- > > 1 file changed, 17 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c > > index e748acdd2d31..0f39982c70b1 100644 > > --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c > > +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c > > @@ -1004,24 +1004,39 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) > > } > > > > if (udphy->status == UDPHY_MODE_NONE) { > > + phy_notify_reset(udphy->phy_u3, PHY_NOTIFY_PRE_RESET); > > + > > + rk_udphy_u3_port_disable(udphy, true); > > This change is not described in the commit message. Good catch. I'm not sure when that sneaked in. I will split it into its own follow-up patch. FWIW these two things are a little bit interleaved: resetting the PHY results in disabled clocks, results in SError when dwc3 driver tries to access its registers during the PHY reset. This is worked around by the u3 port disabling, which reroutes the clock. But doing that increases the chance a lot, that the PHY does not start up properly again, which requires the reset notifier bits. Greetings, -- Sebastian