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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-87fea78fedbsm4448464b3a.23.2026.09.28.09.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 09:37:52 -0700 (PDT) Date: Mon, 28 Sep 2026 16:37:44 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Catalin Marinas , Jonathan Corbet , iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, Mark Rutland , Randy Dunlap , Robin Murphy , Shuah Khan , Will Deacon , David Matlack , Jean-Philippe Brucker , Jonathan Cameron , Nicolin Chen , Pasha Tatashin , patches@lists.linux.dev, Samiullah Khawaja , Mostafa Saleh , stable@vger.kernel.org, Vijayanand Jitta Subject: Re: [PATCH v7 4/9] iommu/arm-smmu-v3: Optimize range invalidation for latency Message-ID: References: <0-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> <4-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> <20260928135007.GA1616761@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260928135007.GA1616761@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260928_093754_657242_9D6C9072 X-CRM114-Status: GOOD ( 31.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 28, 2026 at 10:50:07AM -0300, Jason Gunthorpe wrote: > On Mon, Sep 28, 2026 at 01:15:50PM +0000, Pranjal Shrivastava wrote: > > > -/* Used by non INV_TYPE_ATS* invalidations */ > > > -static void arm_smmu_inv_to_cmdq_batch(struct arm_smmu_inv *inv, > > > +/* > > > + * One TLBI command per IOTLB entry, assuming the entries are all at least > > > + * iopte_granule sized. Returns false if too many commands would be needed which > > > + * indicates too high a latency. The threshold is similar to MAX_DVM_OPS in > > > + * arch/arm64/include/asm/tlbflush.h for the 4k PAGE_SIZE. > > > + */ > > > +static bool arm_smmu_cmdq_batch_add_single(struct arm_smmu_device *smmu, > > > + struct arm_smmu_cmdq_batch *cmds, > > > + struct arm_smmu_cmd *cmd, > > > + struct arm_smmu_tlbi *tlbi) > > > +{ > > > + unsigned long num_ops = tlbi->size / tlbi->iopte_size; > > > + unsigned long iova = tlbi->iova; > > > + unsigned long i; > > > + > > > + if (!num_ops || num_ops > 512) > > > + return false; > > > + > > > > Should this be ">= 512"? The old arm_smmu_inv_size_too_big() and > > arm64's __flush_tlb_range_limit_excess() both fall back to a full > > invalidation at exactly 512: > > > > return pages >= (MAX_DVM_OPS * stride) >> PAGE_SHIFT; > > > > 512 is what a walk flush could generate. For example, when > > __arm_lpae_unmap() frees a last-level table on a 4K granule, > > it calls io_pgtable_tlb_flush_walk(iova, SZ_2M, SZ_4K), hence, > > num_ops == 512. > > > > Before this patch that was a single TLBI_NH_ASID/TLBI_S12_VMALL, now > > it becomes 512 VA TLBIs + CMD_SYNC for every 2M table freed on a > > non-RIL SMMU. The same check carries into arm_smmu_tlbi_calc_single() > > later in the series. > > I had set it deliberately like that so that a table flush would issue > singles. That is largely based around the feedback from before that we > shouldn't over invalidate. > > We've been insensitive to that issue in the past, and I'm going to > argue the >= of today's code is a bug as it effectively made alot of > iopgtable actions turn into new full invalidations, while originally > they were range bound singles. > > So I view this choice as a return to the historical behavior before we > started to fix the soft lockup issues. I guess it crept it during one > of the refactorings where we merged the SVA limitation into the main > flow. > Makes sense, thanks. I checked and before the invs rework the only cap was CMDQ_MAX_TLBI_OPS in the SVA notifier; the io-pgtable path issued singles without any limit. > Granted I didn't notice this detail that the current code was 511 not > 512, I will add a remark to the commit message: [...] > The current code switches at 511, but this turns every table removal > into a full invalidation. Change to 512 to try to minimize the amount > of full invalidation. Nit: that holds for a 4K granule. With 16K/64K a table removal is still a full invalidation (2048/8192 ops), and the limit there actually drops from 2047/8191 to 512, so it may be worth incorporating in the remark too. Reviewed-by: Pranjal Shrivastava Thanks, Praan