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[2a02:3100:b2e2:2001:c47f:5a89:3d9a:cd2d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48b380faaeesm12742668f8f.18.2026.10.03.10.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Oct 2026 10:07:25 -0700 (PDT) Date: Sat, 3 Oct 2026 19:07:22 +0200 From: Karl Mehltretter To: Arnd Bergmann Cc: Russell King , Miguel Ojeda , Boqun Feng , Gary Guo , =?utf-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , Onur =?utf-8?B?w5Z6a2Fu?= , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E. McKenney" , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] ARM: rust: Enable Rust support for ARMv5TE Message-ID: References: <20261003093827.77857-1-kmehltretter@gmail.com> <20261003093827.77857-3-kmehltretter@gmail.com> <33197b82-3eff-4c87-b370-c677ca31a02a@app.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <33197b82-3eff-4c87-b370-c677ca31a02a@app.fastmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261003_100728_350073_2F22D853 X-CRM114-Status: GOOD ( 30.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Oct 03, 2026 at 12:45:07PM +0100, Arnd Bergmann wrote: Hi Arnd, > > Kernels that also contain ARMv4 or ARMv4T CPUs are built for the > > lowest architecture and stay excluded. CPU_32v5 also covers the ARMv5T > > ARM1020. C code is already built with -march=armv5te there, so Rust > > matches. > > None of this makes sense to me: The target should not control > the instruction set, that is what the -march= flag is needed for. > Does that not get passed for Rust? No. arch/arm/Makefile only passes --target=arm-unknown-linux-gnueabi, no CPU or feature flags. That target has "+v6" built in, so Rust code in an ARMv7 kernel is built as ARMv6 today. I tried the generic target with CPU flags (libcore for versatile on v7.3-rc1, rustc 1.99.0, CPU arch from the build attributes of core.o): --target=arm-unknown-linux-gnueabi ARMv6, uses uxtb/uxth/sxth/rev --target=arm-unknown-linux-gnueabi -Ctarget-cpu=arm926ej-s still ARMv6 --target=arm-unknown-linux-gnueabi -Ctarget-cpu=arm926ej-s -Ctarget-feature=-v6 ARMv5TE, but every rustc call warns "unstable feature specified for `-Ctarget-feature`: `v6`" --target=armv5te-unknown-linux-gnueabi ARMv5TE --target=armv4t-unknown-linux-gnueabi ARMv4T, no clz, no blx So -Ctarget-cpu can add features but does not remove the +v6. The generic target also declares 64-bit atomics, armv5te and armv4t only 32 bit. Below ARMv6 I only see the separate targets. > > If an ARMv7 kernel includes ARMv6 instructions, that is broken > on ARMv8 CPUs that are lacking the CP15 barriers and swp style > atomics, so that needs to be fixed. The Rust objects from the generic target have no swp and no CP15 access. The atomics go through the C helpers. Building the Rust code of ARMv7 kernels as ARMv7 would be a separate change. I can look at that after this series. > > I don't see what part of rust would depend on ARMv5 instructions, > it should just work on ARMv4T as well, though ARMv4 may be > trickier because missing bx instructions etc. Agreed. !CPU_32v4T only came from the armv5te target, which emits clz and blx. With the armv4t target it can go. ARMv4 has no rustc target. > > > ============================================== > > -``arm`` Maintained ARMv7 Little Endian only. > > +``arm`` Maintained ARMv5TE and ARMv7, Little Endian only. > > Here you exclude ARMv6K and ARMv8-A-aarch32... > [..] > but here you allow it, so I think one of them should change, > Right. A v6K+v7 kernel has CPU_32v7 and gets HAVE_RUST already, a v6K-only kernel does not. No technical reason. I have a patch for v6K-only that I held back until I have a Pi 1, but I guess QEMU suffices. > This looks wrong, the choice between armv5 and armv7 should work > the same way as the choice between armv6 and armv7/v8, if I read > the rustc docs correctly, this should be using the target-cpu= > argument on the generic arm-unknown-linux-gnueabi target. There is no choice between ARMv6 and ARMv7 today. Both get the generic target without flags and so ARMv6 code. And target-cpu= on the generic target does not get below ARMv6, see the table above. That is why I used a separate target for ARMv5. For a v2 of this I would - pick the rustc target next to the -march lines: armv4t for CPU_32v4T, armv5te for CPU_32v5, the generic one from ARMv6K upwards - select HAVE_RUST for everything except CPU_32v4 and plain CPU_V6 - make arch-support.rst say the same I have this running in QEMU on v7.3-rc1 with - sx1 (OMAP310, ARM925T, ARMv4T), omap1_defconfig - versatilepb (ARM926EJ-S), versatile_defconfig - raspi0 (ARM1176), bcm2835_defconfig without ARCH_MULTI_V7 Would that be ok for you? Thanks Karl