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Sun, 4 Oct 2026 13:59:07 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Sun, 4 Oct 2026 13:59:06 -0700 Date: Sun, 4 Oct 2026 13:59:04 -0700 From: Nicolin Chen To: Will Deacon , Jason Gunthorpe CC: , , , , , , , , , Subject: Re: [PATCH v10 06/13] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_KDUMP_ADOPT for kdump kernel Message-ID: References: <20261004163501.GB4064@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261004163501.GB4064@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA0PEPF00000041:EE_|DS0PR12MB7898:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e37410c-e4aa-414f-3023-08df225a5d03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|36860700016|1800799024|376014|7416014|6133799003|18002099003|22082099003|4143699003|11063799006|10067099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3gX5DC6Uiqtcl4KUnuddRYwunv4rCAPQ8S+tR6haf2SsdrodzOgTRB94j8ChtMrNA1RHzI02662gQbX6jjsNxHxtx2Jzgd0u4EP/QBUHj1KlAk9sS7N+U/TpwnBfBVvlHHkk8JJvV/Ik7TYAxRPiD3rVWY2OioD3fWcYwOrP4GnvcioJTOQL2JtVioNBH9DZ1/u/h3HQH+bLvkixHcBUGvZ/4tyciwWMrCWp7PoYFb+kRGmLHwGd58YH/huLED9icccWYgX0DOyXOVfZ1Uogx7HvBANWTqW9qwh19Ex80ltsCYVRbQFZchYZHXIMJU+vtip8EUoEmBTCuyQhK5tm4ZtK6IfWRvkAvWXZQCqaX8XhcJRke8/R08rounNtEd4HNlxXhjMjUlmUD37D6cwDc3Tj9Qk71lxoYQSdzkwcseSNvqXCT5jliSv/xqcKqTkp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2026 20:59:21.0893 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e37410c-e4aa-414f-3023-08df225a5d03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: IA0PEPF00000041.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7898 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261004_135929_545565_76FAECD0 X-CRM114-Status: GOOD ( 23.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Oct 04, 2026 at 01:35:01PM -0300, Jason Gunthorpe wrote: > On Sun, Oct 04, 2026 at 02:25:07PM +0100, Will Deacon wrote: > > > + * - A structural inconsistency at adoption time tosses the entire adoption and > > > + * makes the SMMU fall back to a full reset blocking in-flight DMAs. > > > + * - L2 stream tables are adopted lazily at master-inserting time, to bound the > > > + * peak memory use against a corrupted L1 table; any lazy L2 adoption failure > > > + * rejects that device alone, as its blast radius is bounded to the bus. > > > + * - Only a coherent SMMU (ARM_SMMU_FEAT_COHERENCY) is supported, as the stream > > > + * table adoption is done by memremap with MEMREMAP_WB, which is verified on > > > + * the real hardware. Callers of these functions are responsible for gating > > > + * ARM_SMMU_FEAT_COHERENCY once during the probe. > > > > This is an artificial restriction and not one that I'm wild about for kdump: > > we should be able to support this for non-coherent SMMUs as well. Is there > > anything more to it than using MEMREMAP_WC in that case? > > I've forgotten why it ended up like this, it was some complication > that seemed hard.. MEMREMAP_WC is not the same attribute dma coherent > would have used, I'm not sure we have the right stuff to be able to > flush any write combining buffer? I'm nervous about that at least. > > Remember this is not just reading it but it has to operate like this > after the fact. In handover you wanted to use the dma cohernent > preservation. > > So, I think this restriction is mostly a lack of the right MEMREMAP > flag? It is not insovlable just work outside the scope of this series. I agree that it's safer to defer that to a followup series. It also needs someone who has a non-coherent HW for a full test. On the other hand, this series is tested by folks from multiple organizations, so it's really a needed and verified one. Thanks Nicolin