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[114.72.148.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c4996be6sm2203965b3a.58.2026.10.10.03.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 03:54:24 -0700 (PDT) Date: Sat, 10 Oct 2026 21:54:16 +1100 From: Myria Sarvay To: Marc Zyngier Cc: Michael Reeves , Oliver Upton , Catalin Marinas , Will Deacon , Mark Rutland , Yureka Lilian , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Sven Peter , Janne Grunau , Neal Gompa , asahi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4 Message-ID: References: <20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com> <20261008-apple-m3-m4-kvm-v1-2-7bb4cbf3d63b@gmail.com> <86cxtk2utm.wl-maz@kernel.org> <86bj932ssc.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86bj932ssc.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261010_035426_760614_1961AAE1 X-CRM114-Status: GOOD ( 19.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, (Resending because I forgot to reply all, sorry Marc) On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote: > On Fri, 09 Oct 2026 01:03:57 +0100, > Michael Reeves wrote: > > > > > I can provide the binary (and a few scripts) to test this easily. > > > Should they have been fixed, we can always create a second > > > implementation list to cover the PMU. > > > > Can you please send that so we can try? That would be much > > appreciated, thank you. > > I've sent you (and Yureka) details over IRC. If you need help with > setting things up, let me know directly. > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. I've tested the patches on my M3 Max (t6031-j514c), and without these patches, it SErrors, and with them (and including the M3/M4 MIDRs in the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't SError, and the iso boots correctly to a login getty.