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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e97e8353b1sm35762345ad.39.2026.10.19.01.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 01:02:39 -0700 (PDT) Date: Mon, 19 Oct 2026 08:02:31 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: Jason Gunthorpe , iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Radu Rendec , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , rafael@kernel.org, Danilo Krummrich , driver-core@lists.linux.dev Subject: Re: [PATCH v11 11/16] iommu/arm-smmu-v3: Add CMDQ_PROD_STOP_FLAG to gate CMDQ submissions Message-ID: References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-12-praan@google.com> <20261002164748.GD3481470@ziepe.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261019_010242_807438_8423FB58 X-CRM114-Status: GOOD ( 38.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 06, 2026 at 10:26:41AM -0700, Nicolin Chen wrote: > On Fri, Oct 02, 2026 at 09:11:39PM +0000, Pranjal Shrivastava wrote: > > On Fri, Oct 02, 2026 at 01:47:48PM -0300, Jason Gunthorpe wrote: > > > On Thu, Oct 01, 2026 at 11:03:15AM -0700, Nicolin Chen wrote: > > > > > > > > So we can't issue ATC_INVs during suspend (the EP is already down), nor > > > > > during resume (the SMMU resumes *before* the EP is made active). The EP > > > > > can't use its ATC while suspended, and if it loses power/resets on the > > > > > way back to D0 (from D3cold, or D3hot with No_Soft_Reset=0), it comes > > > > > back with an empty ATC.. same assumption the PCI reset path makes today > > > > > (pci_dev_reset_iommu_prepare()). > > > > > > > > In that case, would the STOP flag be too late? It's only set in > > > > the middle of the SMMU suspend. So, an ATC command (via doamin > > > > invalidation) might be issued prior to the Point of Commitment, > > > > which will be timed out due to the unresponding EP? > > > > > > How can you ever fix that? > > > > The unfortunate reality is that this gap exists in the kernel even > > today.. upstream SMMUv3 has no RPM, so it's always on, while the EPs can > > runtime suspend independently. So an ATC_INV can already be issued to > > an EP that has suspended. I'd argue RPM improves this slightly, since > > once the STOP flag is set everything is elided, so the window closes at > > SMMU suspend instead of never. > > That doesn't sound very convincing though... > All I'm saying is that today, EPs can get suspended without the SMMU ever knowing, making the SMMU aware of it helps with that.. although I agree we need a policy here. > > > How does power management really work, is it expected that the end > > > device is already quieted by its driver? > > > > > > > Yes, power management would topo-sort all dependencies and invoke > > suspend callbacks accordingly, i.e. in our case the suspend callbacks of > > all SMMU clients would be called before the SMMU's suspend callback. > > If that's guaranteed, we should probably -EBUSY the suspend if one > STE isn't aborted. > That'd only work for (ATS-enabled) PCI devices.. for platform devices, the STE stays as is across RPM by design (no ATC, and the TLB/CFG state is covered by the invalidate-all on resume). > > > Could the first step in power management install a blocked STE? Then > > > we don't have to worry about ATC desync and that automatically stops > > > generating new ATC invalidations if we go and detact the domains too > > > > > > > Partially.. at SMMU suspend we set GBPA to abort and clear SMMUEN, so > > nothing gets through while the SMMU is off. But that's global and only > > happens after all EPs are down, it doesn't stop ATC_INVs in the window > > Nicolin pointed out. > > > > One way to ensure the ATC state is relying on the PCIe spec to lose ATC > > content during D0 entry from D3cold, or D3hot with No_Soft_Reset=0). > > > > Another way to enforce this, is to *somehow* ask the endpoint drivers > > disable ATS during *their* suspend, i.e. in the EP's driver's suspend > > they could call pci_disable_ats or a better suited helper from pci core > > and the in the pm_resume / rpm_resume they could call it's equivalent > > pci_enable_ats, counterpart ensuring a clean ATS state. Or maybe the > > pci_enable/disable_ats is used by IOMMU drivers only. > Can't the PCI core call it too? I agree the endpoint drivers may not be aware of ATS, but there should be some way for us to flush + disable the ATC after the EP driver's suspend & before the EP sleeps (and so before the SMMU's suspend is called)? > > pci_dev_reset_iommu_prepare/done() pair (with slight refactoring) in EP's > > suspend/resume? > > That sounds right to me, though a different API for suspend/resume > will be required. And call them in pci_pm_runtime_suspend/resume() > maybe. > Ack. Praan