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Mon, 19 Oct 2026 02:14:33 -0700 (PDT) X-Received: by 2002:a05:7300:e5c2:b0:352:4f11:8118 with SMTP id 5a478bee46e88-361a3813baamr10646746eec.40.1792401272643; Mon, 19 Oct 2026 02:14:32 -0700 (PDT) Received: from oss.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3607bc950f9sm34130421eec.0.2026.10.19.02.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 02:14:31 -0700 (PDT) Date: Mon, 19 Oct 2026 14:44:21 +0530 From: Mohd Ayaan Anwar To: Alex Elder Cc: maxime.chevallier@bootlin.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Daniel Thompson , mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, hkallweit1@gmail.com, linux@armlinux.org.uk, richardcochran@gmail.com, p.zabel@pengutronix.de, peppe.cavallaro@st.com, joabreu@synopsys.com, lorenzo.bianconi@oss.qualcomm.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 5/5] net: stmmac: support the TC9564 SoC Message-ID: References: <20261019030129.1470307-1-elder@riscstar.com> <20261019030129.1470307-6-elder@riscstar.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261019030129.1470307-6-elder@riscstar.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDAzNiBTYWx0ZWRfX8584aXqGEo/z ZTt41Rvl0KL5Xqf/sz+v9Xv5vliH8TlHd+RCoOYKmrHE8nESVOInpa/H0RZg2+LRWo3M29Aignq K2e9pZO+A043w1JZcWKRyI7F0S2r4JXCSB1nDk/HZNRDFJGu+bZXtH38PwuXVzvCwBVV8I7UjBn 8BhsKkUvhSe0apdENnJ1xuxHWLWFlE1MJONOImb8HWLzBzUQEMyHrBEscfxTAt3+5Agbgt5Z79K dOmWesfl9OCHeSTf91ZF36jeNa4v4NPWUIuR4gKdBoLB07RdjoPomi2zqNmKOwJKsp04Mxs0ChT fLhxSZlxall5uslN0JmvsgSPPaEzaVdbIkfBRkRo/gP+SxQ0LFvXroagnixAHJSWNeqmT8zzcfE h+Z10JA0tGqaGuBIGJGYDSgZNLtOUAUGnTmT/gb9fzEzW111TS7i0ccstG/mqzBcU5ekcepKvg+ xuhxkvbrSPMoJEuzdDw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDAzNiBTYWx0ZWRfX8M8CimLkdmoI 1ZQ4cgJhdwR5tgHB+fSH9opcX4t70GFexCWQ3vV6HqzbcQsuwPBv/TwWSyv69/IOAdtugI8+WHD oh/YL75rY2OnNxPuB23JLIvqBFSTcIU= X-Proofpoint-GUID: Ac_BkEsrCWIWGj357Q6VircKnCoCGNNt X-Authority-Analysis: v=2.4 cv=K/+3jCWI c=1 sm=1 tr=0 ts=6ad5df7a cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=ee_2aqc6AAAA:8 a=0b3DlNp43F3Af77sOdMA:9 a=CjuIK1q_8ugA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=VOpmJXOdbJOWo2YY3GeN:22 X-Proofpoint-ORIG-GUID: Ac_BkEsrCWIWGj357Q6VircKnCoCGNNt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_03,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610190036 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261019_021435_845018_34A29B8B X-CRM114-Status: GOOD ( 31.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Alex, On Sun, Oct 18, 2026 at 10:01:28PM -0500, Alex Elder wrote: > From: Daniel Thompson > > Add support for the Ethernet XGMAC functionality present in the > Toshiba TC9564 SoC. > > The TC9564 is a fairly complex chip that attaches to a host via > the upstream port of a PCIe switch it implements. That switch > has three downstream ports, and one of those has an embedded PCI > endpoint. The PCI endpoint implements two PCI functions, and a > 10 Gbps-capable XGMAC interface is attached to each. > > The TC9564 implements additional peripherals, and access to them > is provided by a PCI endpoint bus associated with BAR 4 of the > first PCI function. A PCI driver sets up the PCI function for > use, and peripherals using the bus use platform drivers, matched > by compatible string. > > We use the pci-ep-bus approach for the stmmac driver as well, with > each PCI function exposing access to its BAR 4 via an endpoint bus. > The XGMAC device is defined within a pci-ep-bus node, and is bound > to the platform driver based on its compatible string. > > Signed-off-by: Daniel Thompson > Co-developed-by: Alex Elder > Signed-off-by: Alex Elder > --- > ... > +/* Fields and values for the EMACTL registers */ > +#define EMAC_SP_SEL_MASK GENMASK(3, 0) > +#define SP_SEL_2500BASEX 4 > +#define SP_SEL_SGMII_1000M 5 > +#define SP_SEL_SGMII_100M 6 > +#define SP_SEL_SGMII_10M 7 > +#define EMAC_PHY_INF_SEL_MASK GENMASK(5, 4) > +#define PCS_CLK_PHY 1 /* Clock from PHY */ > +#define EMAC_INV_SGM_SIG_DET BIT(6) /* 1 = polarity inverted */ > +#define EMAC_LPIHWCLKEN BIT(8) /* 1 = low power mode */ > +#define EMAC_INIT_DONE BIT(21) > + Nit: extra tab before BIT(8) and BIT(21). > + > +#define PMA_HWT_REFCK_R_EN 0x1080 > +#define PMA_HWT_REFCK_TERM_EN 0x1090 > +#define PMA_HWT_REFCK_STRIDE 0x0014 > + > +#define PMA_COMM_CFG_0_1 0x1888 > +#define PMA_COMM_CFG_0_1_STRIDE 0x0008 Nit: extra tab before 0x1090 and 0x0008. > + > +static int tc9564_probe_config_dt(struct tc9564_data *td) > +{ > + struct platform_device *pdev = to_platform_device(td->dev); > + struct device_node *np = td->dev->of_node; > + struct plat_stmmacenet_data *plat; > + phy_interface_t phy_interface; > + struct device *dev = td->dev; > + int ret; > + > + ret = device_get_phy_mode(dev); > + if (ret < 0) > + return -ENODEV; > + phy_interface = ret; > + Nit: I think the call to devm_stmmac_probe_config_dt() will get the PHY mode from firmware and store it in plat_dat->phy_interface so this is probably redundant. > + /* The platform structure is allocated with devm_kzalloc() */ > + plat = devm_stmmac_probe_config_dt(pdev, td->res.mac); > + if (IS_ERR(plat)) > + return PTR_ERR(plat); > + > +static int tc9564_dwmac_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct tc9564_data *td; > + struct device_node *np; > + struct regmap *regmap; > + int ret; > + > + td = devm_kzalloc(dev, sizeof(*td), GFP_KERNEL); > + if (!td) > + return -ENOMEM; > + > + td->dev = dev; > + > + np = dev_of_node(dev); > + regmap = syscon_regmap_lookup_by_phandle_args(np, > + "toshiba,config-syscon", > + 1, &td->emac_ctl_offset); > + if (IS_ERR(regmap)) > + return dev_err_probe(dev, PTR_ERR(regmap), > + "failed to get config regmap\n"); > + td->config_regmap = regmap; > + > + ret = tc9564_reset_init(td); > + if (ret) > + return dev_err_probe(dev, ret, "failed to initialize resets\n"); > + > + ret = tc9564_clock_init(td); > + if (ret) > + return dev_err_probe(dev, ret, "failed to initialize clocks\n"); > + > + ret = tc9564_probe_config_dt(td); > + if (ret) > + return ret; > + > + ret = stmmac_get_platform_resources(pdev, &td->res); > + if (ret) > + return dev_err_probe(dev, ret, > + "failed to initialize stmmac resources\n"); > + > + tc9564_mac_enable(td); > + > + ret = stmmac_dvr_probe(dev, td->plat, &td->res); > + if (ret) { > + ret = dev_err_probe(dev, ret, "failed stmmac probe\n"); > + goto err_disable_mac; > + } Nit: Could this use devm_stmmac_pltfr_probe() and drop tc9564_dwmac_remove()? tc9564_mac_disable() could be registered as the priv->plat->exit callback. > + > + return 0; > + > +err_disable_mac: > + tc9564_mac_disable(td); > + > + return ret; > +} > + Ayaan