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[34.140.183.197]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a210473567sm56280825e9.12.2026.10.23.00.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 00:59:32 -0700 (PDT) Date: Fri, 23 Oct 2026 08:59:29 +0100 From: Vincent Donnefort To: Fuad Tabba Cc: maz@kernel.org, oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, kernel-team@android.com, tabba@google.com Subject: Re: [PATCH v2 2/4] KVM: arm64: pkvm: Fix missing reset of GICv3 LRs Message-ID: References: <20261022140048.2522787-1-vdonnefort@google.com> <20261022140048.2522787-3-vdonnefort@google.com> <20261022173604.3710390-1-fuad.tabba@linux.dev> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261022173604.3710390-1-fuad.tabba@linux.dev> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_005937_083374_378C356B X-CRM114-Status: GOOD ( 30.46 ) X-Spam-Score: -17.6 (-----------------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-23.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Oct 22, 2026 at 06:36:04PM +0100, Fuad Tabba wrote: > Hi Vincent, > > On Thu, 22 Oct 2026 15:00:46 +0100, Vincent Donnefort wrote: > > The vGIC LRs are architecturally UNKNOWN when the CPU boots or resumes. > > However, in protected mode, only the used ones are reset, because the > > HVC __vgic_v3_init_lrs() is never called: > > Could you say here what happens to a guest when an LR isn't reset, as I > asked on v1? Without this series, on QEMU changed to leave a pending > vINTID 100 in the top LR at CPU reset, the guest warns "Unexpected > interrupt (irqnr 100)". With only the EOI bit set there, the npVM > doesn't print anything in 150 seconds, since the maintenance interrupt > is asserted on every entry. With that in the message, could you also > bring back the Cc: stable you had on v1? Sorry I missed that. Actually I don't know if this should be backported. I believe it was working until now because all SoCs do reset their LRs even though they don't have to do it. -- Vincent > > [...] > > Then, cpu_hyp_init() is only called from init_subsystems and > > kvm_arch_enable_virtualization_cpu(). Remove the kvm_hyp_initialized > > gate: when pKVM is enabled, the cpu_hyp_reset() will just return an > > error while for other modes, we already know kvm_hyp_initialized is > > false at this point. > > In init_subsystems(), only the CPU that ran do_pkvm_init() returns an > error here. The others are still on the hyp stub, which returns 0 for > HVC_RESET_VECTORS, so they go through the full init. Could you reword > this part? > > [...] > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > [...] > > static void cpu_hyp_reinit(void) > > { > > - cpu_hyp_reset(); > > - cpu_hyp_init_context(); > > - cpu_hyp_init_features(); > > + if (!cpu_hyp_reset()) { > > + cpu_hyp_init_context(); > > + cpu_hyp_init_features(); > > + } else { > > + if (WARN_ON(!__this_cpu_read(kvm_hyp_initialized))) > > + return; > > + } > > Could you make this "} else if (WARN_ON(...)) {", as elsewhere in > arm.c? > > > + > > + /* > > + * Even if the hypervisor didn't allow resetting the vectors we can > > + * reset what we have access to. > > + */ > > nit: "what we have access to" is the LRs, so I'd name them. > > With the above addressed: > Reviewed-by: Fuad Tabba > Tested-by: Fuad Tabba > > Cheers, > /fuad