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24 Oct 2026 06:19:20 -0700 Date: Sat, 24 Oct 2026 16:19:18 +0300 From: Andy Shevchenko To: Chen-Yu Tsai Cc: James Hilliard , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Jernej Skrabec , Samuel Holland , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 2/3] serial: 8250_dw: configure the Allwinner H616 UART Message-ID: References: <20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com> <20261023-submit-h616-uart-fifo-v1-v1-2-e4a3bae2eba8@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261024_061925_384997_530785D7 X-CRM114-Status: GOOD ( 19.43 ) X-Spam-Score: -4.5 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-4.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Sat, Oct 24, 2026 at 10:10:33PM +0900, Chen-Yu Tsai wrote: > On Sat, Oct 24, 2026 at 12:12 AM James Hilliard > wrote: > > On Fri, Oct 23, 2026 at 2:44 AM Andy Shevchenko > > wrote: > > > On Fri, Oct 23, 2026 at 01:33:50AM -0600, James Hilliard wrote: ... > > > > /* Internal 8250 only */ > > > > UART_PORT_AIROHA = 124, > > > > UART_PORT_AIROHA_HS = 125, > > > > + UART_PORT_DW_APB_256 = 126, > > > > > > Why? Besides the poorly chosen name, what prevents us from modifying the > > > corresponding parameters at probe time by leaving the one of the existing > > > types? > > > > The new type was primarily a way to reuse the core's FIFO configuration > > table, including the RX trigger mapping. H616 uses thresholds of 1, 64, > > 128 and 254 bytes, whereas PORT_16550A maps the same FCR bits to 1, 4, 8 > > and 14 bytes. Overriding only fifosize and tx_loadsz would leave > > rx_trig_bytes reporting and selecting the wrong thresholds. > > > > The core already has get_rxtrig/set_rxtrig callbacks, though. I'll rework > > this to retain PORT_16550A, supply the H616 FIFO parameters during setup, > > and use those callbacks for the correct trigger mapping. > > Please consider just taking the FIFO size from the DT. On some chips > not every UART has the same size FIFO, so we already need to deal with > it. > > Also, FIFO size is a standard UART DT property, though somehow not included > for dw-uart. FWIW, it supports all standard properties for UART. Check what uart_read_port_properties() does. -- With Best Regards, Andy Shevchenko