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Thu, 5 Nov 2026 15:54:18 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Thu, 5 Nov 2026 15:54:14 -0800 Date: Thu, 5 Nov 2026 15:54:12 -0800 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v9 14/25] iommu/arm-smmu-v3-kvm: Shadow the command queue Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-15-smostafa@google.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261015200903.2735565-15-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|SACPR12MB275847:EE_ X-MS-Office365-Filtering-Correlation-Id: 1388204c-89a7-4123-8bb0-08df3b9821dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|23010399003|376014|1800799024|82310400026|36860700016|11063799006|4143699003|56012099006|261102123227099003|261021121427099003|261026121527099003|261021135927099003|18002099003|22082099003|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nusorx8oNSwZhRq6x7omkLmH4DDLHNbC5xlMRh+hE/Q2VTz7YOdtPjmq8nQ/K16DWJFLIMzb+BUT+grXZm21yJ89wAZB3PpXwVMbYpeeFtOFe7dF+WEVJbnbTqzQeA1tmM6emIdN/aurInwa6LwIlQlwIUOFHF7OhBFsM565VHqoFntPKvLvByCZ8dZJ+SSFaOnc3557BD/itZ7oTBWF5jxzjsEhq3N4NXGUYaos0jM+M4rVaECd5bZ0AI22VSI+BLjMqzaswAngkYX0MhxEwByoIEaCVwS//PJxtC5U1Z/3J68kUHVUcX3Ha12MSYiAzJkMlxoj9Cb2uocBqEzLIQtoJve4NZQOD426G3Ck5yvh38bWtPdjb/egPoF8T+MJxQzBO1rklaY05WXGE1buMWaR0LvVCGVK4YNR7b7h0Y9E60GdICA1qYZ4d7UGbadx X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 23:54:29.7926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1388204c-89a7-4123-8bb0-08df3b9821dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SACPR12MB275847 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261105_155535_453896_F168C1FA X-CRM114-Status: GOOD ( 18.73 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Oct 15, 2026 at 08:08:45PM +0000, Mostafa Saleh wrote: > At boot, allocate a command queue per SMMU which is used as a shadow > by the hypervisor. > > The command queue size is 64K which is more than enough, as the > hypervisor would consume all the entries per a command queue prod > write, which means it can handle up to 4096 at a time. > > Then, the host command queue needs to be pinned in a shared state, so > it can't be donated to VMs, and avoid tricking the hypervisor into > accessing them. This is done each time the command queue is enabled, > and undone each time the command queue is disabled. > The hypervisor won't access the host command queue when it is disabled > from the host. > > Signed-off-by: Mostafa Saleh Reviewed-by: Nicolin Chen With some nits: > @@ -23,6 +25,15 @@ static size_t kvm_arm_smmu_cur; > static void __init kvm_arm_smmu_array_free(void) > { > int order; > + int i; > + > + for (i = 0 ; i < kvm_arm_smmu_cur ; ++i) { s/ ;/;/g > @@ -158,6 +268,14 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > break; > /* Passthrough the register access for bisectability, handled later */ > case ARM_SMMU_CMDQ_BASE: > + if (is_write) { > + /* Not allowed by the architecture */ > + if (is_cmdq_enabled(smmu)) > + break; Sashiko reported the same WARN_ON issue. You might want to confirm. > @@ -170,9 +288,16 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > break; > > if (is_write) { > + bool last_cmdq_en = is_cmdq_enabled(smmu); Maybe cmdq_was_enabled (local) and cmdq_is_enabled (helper) Nicolin