From: Alexandre Marquet <tb@a-marquet.fr>
To: Doug Anderson <dianders@chromium.org>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Luca Ceresoli <luca.ceresoli@bootlin.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Jingoo Han <jingoohan1@gmail.com>,
Inki Dae <inki.dae@samsung.com>,
Seung-Woo Kim <sw0312.kim@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Peter Griffin <peter.griffin@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Jessica Zhang <jesszhan0024@gmail.com>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org,
Lukas Timmermann <linux@timmermann.space>,
Henrik Grimler <henrik@grimler.se>,
Hendrik Noack <hendrik-noack@gmx.de>
Subject: Re: [PATCH 3/3] drm/panel_edp: Add SEC LTL101DL02-002 panel
Date: Fri, 30 Oct 2026 22:59:51 +0100 [thread overview]
Message-ID: <auUTV87eElVyIeTw@laptop-218> (raw)
In-Reply-To: <CAD=FV=VV82NG1CAL9DtLeDYQdjC9Su6nYfLYbjzmhzEY9a0JSg@mail.gmail.com>
Hi,
Le Thu, Oct 29, 2026 at 04:27:30PM -0700, Doug Anderson a écrit :
> Hi,
>
> On Thu, Oct 29, 2026 at 1:55 PM Alexandre Marquet <tb@a-marquet.fr> wrote:
> >
> > > > diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
> > > > index 94bc54c3833a..c92985363093 100644
> > > > --- a/drivers/gpu/drm/panel/panel-edp.c
> > > > +++ b/drivers/gpu/drm/panel/panel-edp.c
> > > > @@ -2198,6 +2198,8 @@ static const struct edp_panel_entry edp_panels[] = {
> > > > EDP_PANEL_ENTRY('L', 'G', 'D', 0x0778, &delay_200_500_e200_d200, "134WT1"),
> > > > EDP_PANEL_ENTRY('L', 'G', 'D', 0x07fe, &delay_200_500_e200_d200, "LP116WHA-SPB1"),
> > > >
> > > > + EDP_PANEL_ENTRY('S', 'E', 'C', 0x9c0f, &delay_200_500_e50, "LTL101DL02-002"),
> > > > +
> > >
> > > It would also be good to note in the commit message where you got the
> > > timings from. Datasheet? Downstream code? Guessing?
> >
> > Both downstream code and guessing, as I could not get my hand on a
> > datasheet. I will add an explanation to the commit description.
> >
> > Basically, the downstream code waits: at least 500ms before toggling the LCD_EN
> > GPIO for power on; and 200ms after. I matched the 200ms to the hpd_absent
> > delay, since in panel-edp.c, hpd_absent is also the delay that happens
> > right after enabling the LCD regulator (or toggling the enable GPIO, as
> > appropriate). Similarly, the unprepare delay is called just before
> > enabling the LCD regulator, through panel_edp_wait(), which matches the
> > way the 500ms delay is used in the downstream code.
> >
> > For the enable delay, I went with the smallest value that would still
> > work, but I admit that I did not try anything below 50ms.
> >
> > >
> > > I had my AI agent take a look for itself. It found evidence suggesting
> > > the enable delay should be 97ms, not 50ms. The other ones seem to be
> > > OK.
> >
> > In the downstream code, 97ms is the delay used before setting the
> > backlight on. My understanding is that this should be used elsewhere
> > (e.g.: in the backlight node of the device's DTS).
>
> I don't believe I've ever seen a delay in the backlight node of the
> device's DTS, so that sounds wrong.
I was referring to the post-pwm-on-delay-ms property of pwm-backlight.
But I tested without this property, and with .enable set to 97ms, and
could not find any difference in behaviour.
>
> The .enable delay here is described as:
>
> /**
> * @enable: Time for the panel to display a valid frame.
> *
> * The time (in milliseconds) that it takes for the panel to
> * display the first valid frame after starting to receive
> * video data.
> *
> * This is (T6-min + max(T7-max, T8-min)) on eDP timing diagrams or
> * the delay after link training finishes until we can turn the
> * backlight on and see valid data.
> */
>
> That sounds like exactly what you're looking for, no?
Indeed. Also having the 97ms value from the downstream code in .enable
removes the guessing associated with the 50ms in my initial proposal. So
I will implement this in v2.
Any preference as to where I should put the new delay_200_500_e97
panel_delay struct? I was thinking after delay_200_500_e80_d50, but
I noticed that the delays are not strictly in alphabetical order.
Thank you again for your review,
Best regards,
Alex.
next prev parent reply other threads:[~2026-10-30 22:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 12:01 [PATCH 0/3] DRM Google Nexus 10 display support Alexandre Marquet via B4 Relay
2026-10-27 12:01 ` [PATCH 1/3] drm/bridge: analogix_dp: deassert DP_PHY_PD on power-on for exynos Alexandre Marquet via B4 Relay
2026-10-29 8:27 ` Marek Szyprowski
2026-10-27 12:01 ` [PATCH 2/3] drm/exynos: exynos_dp: change poweron/off to encoder enable/disable Alexandre Marquet via B4 Relay
2026-10-29 8:28 ` Marek Szyprowski
2026-10-27 12:01 ` [PATCH 3/3] drm/panel_edp: Add SEC LTL101DL02-002 panel Alexandre Marquet via B4 Relay
2026-10-28 16:34 ` Doug Anderson
2026-10-29 20:55 ` Alexandre Marquet
2026-10-29 23:27 ` Doug Anderson
2026-10-30 21:59 ` Alexandre Marquet [this message]
2026-10-30 23:37 ` Doug Anderson
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