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From: Niklas Cassel <cassel@kernel.org>
To: Florian Fainelli <florian.fainelli@broadcom.com>
Cc: linux-kernel@vger.kernel.org, Damien Le Moal <dlemoal@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Ray Jui <rjui@broadcom.com>,
	Scott Branden <sbranden@broadcom.com>,
	Broadcom internal kernel review list
	<bcm-kernel-feedback-list@broadcom.com>,
	Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Tejun Heo <tj@kernel.org>,
	Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>,
	"open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)"
	<linux-ide@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	"moderated list:BROADCOM IPROC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:GENERIC PHY FRAMEWORK" <linux-phy@lists.infradead.org>
Subject: Re: [PATCH v4 0/6] Fix SATA support for NSP SoCs
Date: Mon, 2 Nov 2026 17:52:59 +0100	[thread overview]
Message-ID: <aui_68Kxlpr7zdyn@ryzen> (raw)
In-Reply-To: <20261029212513.4126083-1-florian.fainelli@broadcom.com>

Hello Florian,

On Thu, Oct 29, 2026 at 02:25:07PM -0700, Florian Fainelli wrote:
> This patch series fixes SATA on the Northstar Plus (BCM58xxx/8831x)
> which was broken due to a number of things:
> 
> - the SATA PHY assumed separate PCB windows when a shared one is used
>   for this generation of SoCs
> - the clock/reset (IDM) was not being configured by the driver which
>   meant that depending upon what the boot loader did, or did not, we
>   could have had the AHCI controller still in reset by then
> - on some reference boards, the AHCI controller is not DMA coherent,
>   assuming so leads to all sorts of timeouts, data corruption, etc.
> 
> Since this touches several subsystems: DT, PHY, AHCI and DTS, I would be
> keen on having Damien merge all of those via his tree if acceptable by
> the DT and PHY maintainers, I am OK either way for Broadcom SoC.

Patch 2 (after we get an R-b from DT maintainers) and patch 3 can go via
libata tree, but the normal way would be for phy changes to go via PHY
tree and device tree changes usually go via arm-soc (and lately it seems
to go via a broadcom specific tree first).


Kind regards,
Niklas


      parent reply	other threads:[~2026-11-02 16:53 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-29 21:25 [PATCH v4 0/6] Fix SATA support for NSP SoCs Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 1/6] phy: broadcom: brcm-sata: Keep NSP ports in the shared PCB window Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 2/6] dt-bindings: ata: sata-brcm: Describe the NSP IDM registers Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 3/6] ata: ahci_brcm: Initialize the NSP interface clock and reset Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 4/6] ARM: dts: broadcom: Add the NSP SATA IDM registers Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 5/6] ARM: dts: broadcom: Use noncoherent SATA DMA on BCM958625HR Florian Fainelli
2026-10-29 21:25 ` [PATCH v4 6/6] ARM: dts: broadcom: Enable SATA " Florian Fainelli
2026-11-02 16:52 ` Niklas Cassel [this message]

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