From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69B09606E032 for ; Mon, 2 Nov 2026 15:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=S6vsOCf9; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=X0TlLx/+ DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Unsubscribe-Post:List-Owner; bh=rIIz/gtfC2Y+ir/ymx8Qwz0qEnZD5kOfLUgExDZlSUE=; b=S6vsOCf9K/tD0hqEnI9ZUN/3XQ Q9a3NxTpG+Bku/bxnjVJg8kwlJw+2gAFc8uiCAfn8FfNA0KXsI5HLqzlwxf52pxWa/XXGmxyDNch9 bx7ZirOp1L6It4OPa6krxOCaj4PfzpCLO/45d5WE1dUOsq5xyCSKHIIl1qTG4gv19rQsyfFSnrpci Sc5npotKF7odapEIlw7/uRnJFUM/Jtbn7X0wdJCct8vfACH4BFIHxgYo2IHYe+IRR1T51vHEA+J7K HslJTxhXWC+48JYuBpDy0nLDSx52zViGCKTY2b+urvcjpEsktRhr3fcKHVT9uoQlBYCe+BosIf8Fa 98+T5tbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xNuOh-0000000HE6P-43nZ; Mon, 02 Nov 2026 15:56:36 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xNuOg-0000000HE62-3T3a for linux-arm-kernel@lists.infradead.org; Mon, 02 Nov 2026 15:56:34 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 44F814369C; Mon, 2 Nov 2026 15:56:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3842E1F00A16; Mon, 2 Nov 2026 15:56:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793634994; bh=rIIz/gtfC2Y+ir/ymx8Qwz0qEnZD5kOfLUgExDZlSUE=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=X0TlLx/+2BqpUJ0O7uF4HJlMVjvUqcctCY4wJh2DmEYtVPJMg/9bWsnMuFoxFMO7/ MHHvPM999easQh4jTVkg75DMRhcS29B06kRPVVmHKc75emzSi00DGtxtv/DxIyQ4yg w9PQDEyAO1LRnGyVBgqgsSIafZzzptaLT4MEa/zEFBFuAXD/5ot8yT8pfKc6e1GYYD AF7yXXmK9NChbzEO1Fv/Tzj0lvMDW+wZbc2tvAum4QhbDU/pVrCQL36pdKP+WiC5eQ SxSj10W/ACEPziCQVHNxjY+RYeC4lNHQrtSIvBcliS/BFJ09TguCFozEEGSZ78+nna JjEmR9ugF0lQQ== Date: Mon, 2 Nov 2026 16:56:28 +0100 From: Lorenzo Pieralisi To: Sascha Bischoff Cc: Marc Zyngier , Thomas Gleixner , Radu Rendec , Timothy Hayes , Catalin Marinas , Jonathan Cameron , "Rafael J. Wysocki" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko AI , stable@vger.kernel.org Subject: Re: [PATCH 04/10] irqchip/gic-v5: Serialise ITS invalidation commands Message-ID: References: <20261102-host_gicv5_fixes-v1-0-743b61626fc5@arm.com> <20261102-host_gicv5_fixes-v1-4-743b61626fc5@arm.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261102-host_gicv5_fixes-v1-4-743b61626fc5@arm.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Mon, Nov 02, 2026 at 01:32:57PM +0000, Sascha Bischoff wrote: > The ITS uses DIDR and EIDR to select the translation to invalidate. > These registers are shared by all interrupts targeting the ITS. Event > invalidation can run concurrently for different IRQs, and device > invalidation can overlap it. The per-IRQ descriptor lock does not > serialise the commands, so one CPU can accidentally issue an > invalidation using another CPU's DeviceID or EventID. "Another CPU's DeviceID or EventID " can probably be explained better (or just removed because it is unclear) I understand there is a link to Sashiko's report but it is worth updating the log IMO. "using the DeviceID or EventID associated with an IRQ that is invalidated on another CPU" or something like that. > Add a raw spinlock to each ITS and hold it across the command register > writes and the STATUSR.IDLE poll for both invalidation paths. A raw > spinlock is required because the forwarding path calls the event Can you please define "the forwarding path" more explicitly ? See above. Thanks, Lorenzo > invalidation helper with the IRQ descriptor lock held. > > Fixes: 57d72196dfc8 ("irqchip/gic-v5: Add GICv5 ITS support") > Reported-by: Sashiko AI > Link: https://sashiko.dev/#/patchset/20261016155741.979985-1-sascha.bischoff@arm.com?part=11 > Cc: stable@vger.kernel.org > Signed-off-by: Sascha Bischoff > --- > drivers/irqchip/irq-gic-v5-its.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v5-its.c b/drivers/irqchip/irq-gic-v5-its.c > index 28e39b065de0e..6d98f3dbe34b6 100644 > --- a/drivers/irqchip/irq-gic-v5-its.c > +++ b/drivers/irqchip/irq-gic-v5-its.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,6 +29,8 @@ > struct gicv5_its_chip_data { > struct xarray its_devices; > struct mutex dev_alloc_lock; > + /* Event and device invalidation commands share DIDR. */ > + raw_spinlock_t inv_lock; > struct fwnode_handle *fwnode; > struct gicv5_its_devtab_cfg devtab_cfgr; > void __iomem *its_base; > @@ -129,6 +132,8 @@ static int gicv5_its_itt_cache_inv(struct gicv5_its_chip_data *its, u32 device_i > eidr = FIELD_PREP(GICV5_ITS_EIDR_EVENTID, event_id); > eventr = FIELD_PREP(GICV5_ITS_INV_EVENTR_I, 0x1); > > + guard(raw_spinlock_irqsave)(&its->inv_lock); > + > its_writeq_relaxed(its, didr, GICV5_ITS_DIDR); > its_writel_relaxed(its, eidr, GICV5_ITS_EIDR); > its_writel_relaxed(its, eventr, GICV5_ITS_INV_EVENTR); > @@ -371,6 +376,9 @@ static int gicv5_its_device_cache_inv(struct gicv5_its_chip_data *its, > FIELD_PREP(GICV5_ITS_INV_DEVICER_EVENTID_BITS, > its_dev->itt_cfg.event_id_bits) | > FIELD_PREP(GICV5_ITS_INV_DEVICER_L1, 0x0); > + > + guard(raw_spinlock_irqsave)(&its->inv_lock); > + > its_writeq_relaxed(its, didr, GICV5_ITS_DIDR); > its_writel_relaxed(its, devicer, GICV5_ITS_INV_DEVICER); > > @@ -1112,6 +1120,7 @@ static int __init gicv5_its_init_bases(void __iomem *its_base, struct fwnode_han > return -ENOMEM; > > mutex_init(&its_node->dev_alloc_lock); > + raw_spin_lock_init(&its_node->inv_lock); > xa_init(&its_node->its_devices); > its_node->fwnode = handle; > its_node->its_base = its_base; > > -- > 2.34.1 >