From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: James Hilliard <james.hilliard1@gmail.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@kernel.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH v7 10/12] serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC
Date: Wed, 4 Nov 2026 12:44:35 +0200 [thread overview]
Message-ID: <ausMk21A5PPAaycx@ashevche-desk.local> (raw)
In-Reply-To: <20261103-submit-h616-uart-fifo-v1-v7-10-c9e248d685c1@gmail.com>
On Tue, Nov 03, 2026 at 02:40:03PM -0700, James Hilliard wrote:
> The A523 UART integration, also used by A527 and T527, has 64-byte FIFOs
> on UART0 and 128-byte FIFOs on UART1 through UART7. Each controller reports
> its TX/RX FIFO depth in bits 31:8 of the FIFO Clock Control register at
> offset 0xf0. The field holds a byte count, not a logarithmic encoding.
>
> Read this field in the sunxi setup callback when platform data does not
> provide a fixed FIFO size. A fixed size takes precedence, so H616 retains
> its 256-byte configuration without accessing FCC. The probe has already
> enabled the clocks and deasserted reset before invoking the callback.
> Leave the FIFO clock-control bits untouched.
>
> Use the shared DesignWare trigger setup to validate the depth and build
> the FIFO-relative threshold table. Invalid depths fail probe before
> registration instead of producing zero or truncated thresholds. The 8250
> core derives the transmit load from the discovered depth.
>
> Select this setup for the A523 compatible. Like H616, this integration
> has Allwinner-specific debug-divisor and RS485 registers overlapping the
> generic DesignWare feature probes. Use the common sunxi PIO setup,
> BUSY-safe integer divisor programming and software RS485 handling. Keep
> the APB clock gate enabled during termios updates with SKIP_SET_RATE.
...
> p->type = PORT_16550A;
> p->flags |= UPF_FIXED_TYPE;
+ Blank line in this patch.
> - p->fifosize = data->pdata->fifo_size;
Perhaps a comment here
/* Apply given FIFO size or try to autodetect it */
> + if (data->pdata->fifo_size) {
> + p->fifosize = data->pdata->fifo_size;
> + } else {
> + u32 fcc = dw8250_readl_ext(p, SUNXI_UART_FCC);
> +
> + p->fifosize = FIELD_GET(SUNXI_UART_FCC_FIFO_DEPTH, fcc);
> + }
Add a blank line here in the previous patch.
> up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT | UART_CAP_AFE;
...
Otherwise LGTM.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-11-04 10:44 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 21:39 [PATCH v7 00/12] serial: 8250_dw: share RX trigger setup and describe Allwinner UARTs James Hilliard
2026-11-03 21:39 ` [PATCH v7 01/12] serial: 8250_dw: select port setup through platform data James Hilliard
2026-11-03 21:39 ` [PATCH v7 02/12] serial: 8250: widen RX trigger byte counts to 16 bits James Hilliard
2026-11-03 21:39 ` [PATCH v7 03/12] serial: 8250: share the RX trigger conversion helper James Hilliard
2026-11-03 21:39 ` [PATCH v7 04/12] serial: 8250: expose RX trigger controls for custom callbacks James Hilliard
2026-11-03 21:39 ` [PATCH v7 05/12] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth James Hilliard
2026-11-04 10:40 ` Andy Shevchenko
2026-11-03 21:39 ` [PATCH v7 06/12] dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 James Hilliard
2026-11-04 10:59 ` Andre Przywara
2026-11-04 18:07 ` James Hilliard
2026-11-03 21:40 ` [PATCH v7 07/12] serial: 8250_dw: configure the Allwinner H616 UART James Hilliard
2026-11-04 10:42 ` Andy Shevchenko
2026-11-03 21:40 ` [PATCH v7 08/12] arm64: dts: allwinner: h616: describe the UART integration James Hilliard
2026-11-04 8:11 ` Krzysztof Kozlowski
2026-11-03 21:40 ` [PATCH v7 09/12] dt-bindings: serial: snps-dw-apb-uart: add Allwinner A523 James Hilliard
2026-11-03 21:40 ` [PATCH v7 10/12] serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC James Hilliard
2026-11-04 10:44 ` Andy Shevchenko [this message]
2026-11-03 21:40 ` [PATCH v7 11/12] arm64: dts: allwinner: a523: describe the UART integration James Hilliard
2026-11-04 8:12 ` Krzysztof Kozlowski
2026-11-03 21:40 ` [PATCH v7 12/12] serial: 8250_dw: configure RX trigger thresholds for Octeon James Hilliard
2026-11-04 10:48 ` Andy Shevchenko
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