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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b7da62edb4sm270902255e9.1.2026.11.09.02.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 02:56:14 -0800 (PST) Date: Mon, 9 Nov 2026 10:56:10 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com Subject: Re: [PATCH v9 13/25] iommu/arm-smmu-v3-kvm: Add MMIO emulation Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-14-smostafa@google.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261109_025618_993657_0F9A61ED X-CRM114-Status: GOOD ( 20.32 ) X-Spam-Score: -17.6 (-----------------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-13.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Nov 05, 2026 at 03:04:52PM -0800, Nicolin Chen wrote: > On Thu, Oct 15, 2026 at 08:08:44PM +0000, Mostafa Saleh wrote: > > +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > > + struct user_pt_regs *regs, > > + u64 esr, u32 off) > > +{ > > + bool is_write = esr & ESR_ELx_WNR; > > + unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); > > + int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; > > + const u64 read_write = -1ULL; > > + const u64 no_access = 0; > > + u64 mask = no_access; > > + const u64 read_only = is_write ? no_access : read_write; > > + bool is_xzr = (rd == 31); > > + u64 val = is_xzr ? 0 : regs->regs[rd]; > > + > > + switch (off) { > > + case ARM_SMMU_IDR0: > > + if (len != sizeof(u32)) > > + break; > > Maybe add a small helper to list all 64-bit registers: > > static unsigned int smmu_reg_width(u32 off) > { > switch (off) { > case ARM_SMMU_CMDQ_BASE: > case ARM_SMMU_STRTAB_BASE: > case ARM_SMMU_EVTQ_BASE: > case ARM_SMMU_PRIQ_BASE: > case ARM_SMMU_EVTQ_IRQ_CFG0: > case ARM_SMMU_PRIQ_IRQ_CFG0: > case ARM_SMMU_GERROR_IRQ_CFG0: > return sizeof(u64); > default: > return sizeof(u32); > } > } > > Then it'd be tighter by testing the width once, prior to switch (off)? Makes sense, I will try that. > > > + /* Allowed RO 32 bit registers. */ > > + case ARM_SMMU_IIDR: > > + case ARM_SMMU_IDR5: > > + case ARM_SMMU_IDR3: > > + case ARM_SMMU_IDR1: > > + case ARM_SMMU_IRQ_CTRLACK: > > + case ARM_SMMU_GERROR: > > + if (len != sizeof(u32)) > > + break; > > + mask = read_only; > > + break; > > + } > > + > > + if (WARN_ON(!mask)) > > + goto out_ret; > > Your cover letter mentions "WARNs are fatal in the hypervisor". > > Is this WARN_ON fatal? Yes. This is reached if the host does something not emulated: 1) A bug (writing to a RO register, writing STRTAB if SMMU is enabled...) 2) New arch feature not supported. In that case, I'd rather panic here and fix the driver instead of ignoring it which will manifest in a harder to debug symptoms later. Also, this driver only handles the Linux host kernel (which must be built-in in this config) so we can assume how the emulated driver works and what features it use. Thanks, Mostafa > > Nicolin