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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-496c89d8630sm4422045f8f.15.2026.11.09.03.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 03:06:13 -0800 (PST) Date: Mon, 9 Nov 2026 11:06:09 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com Subject: Re: [PATCH v9 13/25] iommu/arm-smmu-v3-kvm: Add MMIO emulation Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-14-smostafa@google.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261109_030616_762217_E9A50824 X-CRM114-Status: GOOD ( 15.37 ) X-Spam-Score: -17.6 (-----------------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-13.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, Nov 06, 2026 at 11:56:34AM -0800, Nicolin Chen wrote: > On Thu, Oct 15, 2026 at 08:08:44PM +0000, Mostafa Saleh wrote: > > +static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr) > > +{ > > + struct hyp_arm_smmu_v3_device *smmu; > > + bool ret; > > + > > + for_each_smmu(smmu) { > > + if (addr < smmu->mmio_addr || addr >= smmu->mmio_addr + smmu->mmio_size) > > + continue; > > + hyp_spin_lock(&smmu->lock); > > + ret = smmu_dabt_device(smmu, regs, esr, addr - smmu->mmio_addr); > > Going through the followup patches, I found this smmu_dabt_device > gets really too big. Perhaps it can be bisect to read and write at > least? Something like: > > static bool smmu_mmio_handler(smmu, regs, esr, off) > { > /* decode ESR: len, rd, xzr; width check */ > if (is_write) > return smmu_mmio_write_handler(smmu, off, len, val); > val = smmu_mmio_read_handler(smmu, off, len); > if (!is_xzr) > regs->regs[rd] = val; > return true; > } Yes, I was wondering about the size of the dabt handler also. I will try this, but that will propably won't cut the size in half. Thanks, Mostafa > > Nicolin