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[35.189.193.160]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49596f9a9ffsm9878242f8f.30.2026.11.09.03.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 03:48:04 -0800 (PST) Date: Mon, 9 Nov 2026 11:47:58 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com Subject: Re: [PATCH v9 16/25] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-17-smostafa@google.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261109_034808_602003_98BD4753 X-CRM114-Status: GOOD ( 19.75 ) X-Spam-Score: -17.6 (-----------------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-18.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, Nov 06, 2026 at 11:08:23AM -0800, Nicolin Chen wrote: > On Thu, Oct 15, 2026 at 08:08:47PM +0000, Mostafa Saleh wrote: > > @@ -385,18 +482,51 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > > */ > > mask = read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP | IDR0_ATS); > > break; > > - /* Passthrough the register access for bisectability, handled later */ > > case ARM_SMMU_CMDQ_BASE: > > + /* > > + * Although allowed to use smaller size, we rely on the SMMUv3 driver > > + * using 64-bit store instruction for simplicity. > > + */ > > + if (len != sizeof(u64)) > > + break; > > if (is_write) { > > /* Not allowed by the architecture */ > > if (is_cmdq_enabled(smmu)) > > The spec says the register is RO when CMDQEN=0. So, maybe it should > be allowed by just ignoring the write? > Yes, that's possible, I am slightly inclined to be more strict here, as this should never happen and if the kernel is buggy or malicous it is better to catch the point it goes wrong rather than trying to debug the side effects of ignoring the write as most likely it will go wrong shortly after (timeouts or commands are ignored causing TLB corruption...). An alternative would be to ignore it and log something, at the moment tracing is supported in EL2, and IIRC, logging to dmesg is also planned. Thanks, Mostafa > > case ARM_SMMU_CMDQ_CONS: > > + if (len != sizeof(u32)) > > + break; > > + if (is_write) { > > + if (WARN_ON(is_cmdq_enabled(smmu))) > > + break; > > Ditto > > Nicolin