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09 Nov 2026 15:10:20 -0800 Date: Tue, 10 Nov 2026 01:10:18 +0200 From: Andy Shevchenko To: James Hilliard Cc: Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v8 06/11] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth Message-ID: References: <20261105-submit-h616-uart-fifo-v1-v8-0-14024d2b184b@gmail.com> <20261105-submit-h616-uart-fifo-v1-v8-6-14024d2b184b@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261105-submit-h616-uart-fifo-v1-v8-6-14024d2b184b@gmail.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261109_151026_500817_7BD27403 X-CRM114-Status: GOOD ( 18.49 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Nov 05, 2026 at 01:52:07PM -0700, James Hilliard wrote: > DW_apb_uart uses receive thresholds of one byte, one quarter full, > one half full and two bytes below full. The generic 16550A table describes > these encodings only for a 16-byte FIFO. For example, the half-full setting > on a 64-byte DW FIFO is reported as eight bytes instead of 32, and a sysfs > request for 32 bytes selects the 62-byte encoding. > > Build a per-port threshold table from the discovered FIFO depth in dwlib > and install receive-trigger callbacks for CPR-described FIFOs, including > LPSS ports. Keep the setup helper available to integrations which obtain > the depth without probing the optional DW registers. Validate that each > threshold is positive and representable before constructing the table. > > Serialize FCR updates with termios and the port lock, acquire a runtime PM > reference before accessing the device, and propagate resume errors without > changing the shadow or hardware. Update only the trigger field so changing > the threshold preserves the FIFO contents. > > The FCR mapping is documented in the DW_apb_uart databook, section 6, > FIFO Control Register. The existing default FCR encoding is unchanged. ... > +static int dw8250_set_rxtrig(struct uart_port *p, u16 bytes) > +{ > + struct dw8250_port_data *pd = p->private_data; > + struct uart_8250_port *up = up_to_u8250p(p); > + int fcr, ret; > + > + fcr = serial8250_bytes_to_fcr(pd->rxtrig_bytes, bytes); > + if (fcr < 0) > + return fcr; > + > + guard(mutex)(&p->state->port.mutex); > + > + PM_RUNTIME_ACQUIRE_IF_ENABLED(p->dev, pm); > + ret = PM_RUNTIME_ACQUIRE_ERR(&pm); > + if (ret) > + return ret; > + > + guard(uart_port_lock_irqsave)(p); > + > + up->fcr &= ~UART_FCR_TRIGGER_MASK; > + up->fcr |= fcr; FIELD_MODIFY() > + /* Changing the trigger alone preserves the FIFO contents */ > + serial_port_out(p, UART_FCR, up->fcr); > + > + return 0; > +} -- With Best Regards, Andy Shevchenko