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Brown" , stable@vger.kernel.org Subject: Re: [PATCH] phy: freescale: phy-fsl-imx8-mipi-dphy: Fix hs_zero underflow Message-ID: References: <20261110120546.6247-1-stefan.ghetu@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261110120546.6247-1-stefan.ghetu@nxp.com> X-ClientProxiedBy: FR4P281CA0102.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:cb::9) To GV2PR04MB12318.eurprd04.prod.outlook.com (2603:10a6:150:32b::19) X-Archived-By: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12318:EE_|VI0PR04MB11937:EE_ X-MS-Office365-Filtering-Correlation-Id: 521ecf40-d37f-4ebd-cf40-08df3f3a791a X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|23010399003|19092799006|11063799006|56012099006|10067099003|261026121527099003|22082099003|18002099003; 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Brown" > > The hs_zero timing is computed as > > n = (144 * (hs_clk_rate / 1000000) - 47500) / 10000; > cfg->m_prg_hs_zero = n < 1 ? 1 : n; > > hs_clk_rate is an unsigned long, so the subtraction is done unsigned and > wraps for any rate below about 330 MHz, where 144 * MHz < 47500. Because > n is a u32, the wrapped value is never seen as negative and the "n < 1" > clamp does not take effect. The garbage value is then truncated into the > 8-bit m_prg_hs_zero register field. At the minimum supported rate of > 80 MHz this programs 199 on 64-bit and 181 on 32-bit, instead of the > intended minimum of 1. > > Make n signed and do the arithmetic in int so the clamp works on both > 32-bit and 64-bit. The divided rate is at most 1500, so 144 * 1500 fits > easily in an int. > > Fixes: f4c8116e294b ("phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs") > Cc: stable@vger.kernel.org > Signed-off-by: Oliver F. Brown > Signed-off-by: Stefan Ghetu Reviewed-by: Laurentiu Palcu -- Thanks, Laurentiu